Vmetro M5210RP-EFF, User Manual, Page: 99 / 130

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Issued June 20, 2007 M5000 Series: User Guide
PCI Slave Images
B-3 PCI Slave Images
The VME_RAI, described in the 'VMEbus Slave Images' section, is also utilized to set up PCI slave
images in the examples below.
PCI Target Enable - Memory & I/O Space
In addition to the configuration registers for the PCI slave images, two control register bits are
essential for mapping PCI bus cycles to VMEbus cycles through the Universe II. The PCI Target
Memory Enable ('MS') and Target IO Enable ('IOS') bits, located in the PCI_CSR register (offset:
0x004), must be set to allow the Universe II to respond to PCI memory and I/O commands.
FIGURE B-2.
Configuration
example for
PCI slave
images
PCI bus VMEbus
PCI Slave Image
# 0
VMEbus A24, D16,
supervisor, data
0x001FFF
0x001000
UNIVERSE IID
0x0000FFF
0x00000000
PCI bus I/O Space
PCI Slave Image
# 1
VMEbus A32, D64, non-
privileged, data, allow
BLT.
VMEbus A32, D32, non-
privileged, data, allow
BLT.
0x3FFFFFFF
0x20000000
0x2FFFFFFF
0x10000000
PCI bus Memory Space.
PCI Slave Image
# 3 (not used)
PCI Slave Image
# 2
0x1FFF.FFFF
0x0000.0000
0x5FFF.FFFF
0x4000.0000
PCI bus Memory Space.
VME Register
Access Image
VMEbus A24, all AM
codes
0x000FFF
0x000000