Vmetro M5210RP-EFF, User Manual, Page: 51 / 130

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Issued June 20, 2007 M5000 Series: User Guide
Secondary and Tertiary PCI Segments
4.2 Secondary and Tertiary PCI Segments
PCI Mode and Speed Configuration
The PCIXCAP and M66EN pins of a PMC module determine which clock speed and protocol (PCI
vs. PCI-X) can be used on the segment. There are five detectable modes of operation: 33/66MHz
PCI and 66/100/133MHz PCI-X.
Configuration switches can be used to:
•
Ground the PCIXCAP signal to force PCI operations, or pull low to inhibit 100/133 MHz
operations by configuration switches.
•
The M66EN signal can also be grounded through in order to inhibit 66MHz PCI operations.
•
Select between 133 and 100 MHz as the maximum operating frequency.
The detected PCIXCAP/M66EN/dip-switches values determine the frequency of the clock
generator for the segment. Table 2-9 on page 17 for dip-switch settings.
Arbitration
Secondary and Tertiary PCI Segments
The built-in PCI-X arbiter of the PCI6540 PCIX-to-PCIX Bridge is used. The arbiter provides two
REQ/GNT pairs to the PMC to support a dual device PPMC.
IDSEL Assignment
Secondary PCI Segment
•
AD[17] is used for the PMC#1 IDSEL
•
AD[18] is used for the PMC#1 IDSELB
•
AD[19] is used for the PCI6540 P2P Secondary Side IDSEL (PCI6540 located in the Processor
Subsystem)
•
AD[20] is used for the PCI6540 P2P Primary Side IDSEL (PCI6540 located between the
Secondary and Tertiary PCI Segments)
Tertiary PCI Segment
•
AD[17] is used for the PMC#2 IDSEL
•
AD[18] is used for the PMC#2 IDSELB
•
AD[19] is used for the PCI6540 P2P Secondary Side IDSEL (PCI6540 located between the
Secondary and Tertiary PCI Segments)
Note – Even if PMCs can only signal that they are either 66 or 133 MHz compliant in PCI-X
mode, the host may decide to run 133 MHz capable boards at a lower frequency (typically
100MHz) if the total number of loads is too high for the system to achieve 133MHz
operations.