Manual VIPA PC-CPU 486
Chapter 4 Deployment of the PC-CPU
HB111E - Rev. 02/32
4-13
//Flags and Frame of 0x1800uL
#ifdef PC_CPU_486_DPM
#define ADR_IM208_KONSISTENZ_INPUT_HANDSHAKE (ADR_IM208_FPG 0x1AE0uL) //Lock input area
#define ADR_IM208_KONSISTENZ_OUTPUT_HANDSHAKE (ADR_IM208_FPG 0x1AE2uL) //Lock output area
#endif
#define ADR_IM208_MMC_IM208K_READ (ADR_IM208_FPG 0x1AE4uL)
#define ADR_IM208_MMC_IM208K_WRITE (ADR_IM208_FPG 0x1AE6uL)
#define ADR_IM208_MMC_CPU_LOCK (ADR_IM208_FPG 0x1AE8uL)
#define ADR_IM208_MMC_IM208K_LOCK (ADR_IM208_FPG 0x1AEAuL)
#define ADR_IM208_IM208K_ALARM_FLAG (ADR_IM208_FPG 0x1AECuL)
#define ADR_IM208_BASP (ADR_IM208_FPG 0x1AEEuL)
#define ADR_IM208_IM208K_KACHEL_OK (ADR_IM208_FPG 0x1AF0uL)
#define ADR_IM208_LED_STATE (ADR_IM208_FPG 0x1AF2uL)
#define ADR_IM208_INFO_GUELTIG (ADR_IM208_FPG 0x1AF4uL)
#define ADR_IM208_HOCHLAUFVERZOEGERUNG (ADR_IM208_FPG 0x1AF6uL)
#define ADR_IM208_FIRMWARE_VERSION (ADR_IM208_FPG 0x1AF8uL) //4Byte
#define ADR_IM208_HWCONF_RET (ADR_IM208_FPG 0x1AFCuL)
#define ADR_IM208_HWCONF_OPC (ADR_IM208_FPG 0x1AFEuL)
#define ADR_IM208_HWCONF_FRAME (ADR_IM208_FPG 0x1B00uL) //256Byte frame length
//to 0x1C00uL
//----------------------------------------------------------------------------
#define ADR_IM208_VBUS_TYPKENNUNG (ADR_IM208_FPG 0x1F00uL) //visible only at DP master (R/W)
#define ADR_IM208_VBUS_STECKPLATZKENNUNG (ADR_IM208_FPG 0x1F02uL) //visible only at DP master (R)
#define ADR_IM208_VBUS_ADRESSOFFSET (ADR_IM208_FPG 0x1F04uL) //visible only at DP master (R)
#define ADR_IM208_VBUS_INTERRUPT_CONFIG (ADR_IM208_FPG 0x1F06uL) //visible only at DP master (R/W)
#define ADR_IM208_VBUS_INTERRUPT_EVENT (ADR_IM208_FPG 0x1F08uL) //visible only at DP master (R/W)
#define ADR_IM208_REGISTER_LED (ADR_IM208_FPG 0x1F0AuL) //visible only at DP master (W)
//(steuert LEDs bei VBUS und page frame FPGAs)
#define ADR_IM208_VBUS_PARAMETERDATEN (ADR_IM208_FPG 0x1FB0uL) //visible only at DP master (R)
#define ADR_IM208_VBUS_DIAGNOSEBEREICH (ADR_IM208_FPG 0x1FD0uL) //visible only at DP master (W)
#define ADR_IM208_VBUS_ALARMSTATUSBEREICH (ADR_IM208_FPG 0x1FF0uL) //visible only at DP master (W)
//to 0x2000uL
//----------------------------------------------------------------------------
/////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////
// Defines for the block administration in the DPRAM
//
// +-----------------+
// | X D B K . . . . | block administration Byte0
// +-----------------+
// | Y L L L L L L L | block administration Byte1
// +-----------------+
//
// D: Data-Bit:
1=ocuppied with data, 0=free
// B: Block-Bit:
1=Block (>= 2Byte), 0=only 1Byte
// K: Consistency-Bit:
1=consistent, 0=not consistent
// X: Semaphore of the CPU:
1=occupied, 0=free
// Y: Semaphore of the DP master:
1=occupied, 0=free
// LLLLLLL: Block length:
0x00..0x7F = 1...128Byte
//
// [The block administrationByte 0 has 4 free Bits. If the block length of LLLLLLL (1..128)
// is not enough, it would be possible to write blocks between (1..2048)
// by using this 4 Bit.]
//
// 4 cases with examples:
//
// 1. This Byte address is not occupied:
// Block administrationByte 0: x 0 x x x x x x
// The next Byte is again a block administrationByte 0 !
//
// 2. There is only 1Byte:
// Block administrationByte 0: x 1 0 x x x x x
// The next Byte is again a block administrationByte 0 !
//
// 3. There is a non-consistent block of 8Byte:
// Block administrationByte 0: x 1 1 0 x x x x
// Block administrationByte 1: x 0 0 0 0 1 1 1 (Block length: 0x07 = 8Byte)
// The following 6Byte are: 0x00
//
// 4. There is a consistent block of 128Byte:
// Block administrationByte 0: x 1 1 1 x x x x
// Block administrationByte 1: x 1 1 1 1 1 1 1 (Block length: 0x7F = 128Byte)
// The following 126Byte are: 0x00
#define BLOCKVERWALTUNG_X 0x80
#define BLOCKVERWALTUNG_D 0x40
#define BLOCKVERWALTUNG_B 0x20
#define BLOCKVERWALTUNG_K 0x10
#define BLOCKVERWALTUNG_Y 0x80
//////////////////////OPCODE for starting the master//////////////////////////////////////////
#define HWCONF_OPC_WITHOUT 0x0003 //Master is started without hardware configuration; from Flash
//////////////////////Marker; shows master ready/////////////////////////////
#define INFO_GUELTIG 0x82 //Pattern for CPU marker for valid address information
Summary of Contents for PC-CPU 486
Page 2: ...Lerrzeichen...
Page 6: ...Content Manual VIPA PC CPU 486 ii HB111E Rev 02 32...
Page 14: ...Chapter 1 Principles Manual VIPA PC CPU 486 1 6 HB111E Rev 02 32...
Page 26: ...Chapter 2 Hardware description Manual VIPA PC CPU 486 2 12 HB111E Rev 02 32...
Page 44: ...Chapter 3 BIOS Register Manual VIPA PC CPU 486 3 18 HB111E Rev 02 32...
Page 64: ...Index Manual VIPA PC CPU 486 A 2 HB111D Rev 02 32 M Stich...