VIPA PC-CPU 486, Manual, Page: 56 / 64

Chapter 4 Deployment of the PC-CPU Manual VIPA CP-CPU 486
4-12 HB111E - Rev. 02/32
This is the event sequence to establish a communication:
PC DP master
1. Start-up Start-up
waits for
OPCODE
2. sets
OPCODE
to start
→
Master starts with
*.2bf-configuration
3. waits for
INFO_GUELTIG
4.
←
sets
INFO_GUELTIG
5. waits for
BASP
= 0
6. sets
BASP
= 0
→
releases all outputs
7. reads I/O data cyclically
←→
creates cyclically an
I/O image of all configured DP
slaves.
In the following you find a C-program to illustrate the access to the
DP master.
/*****************************************************************************
* VIPA GmbH *
* *
* Image of the Profibus DP master in the DPRAM of the PC-CPU 486DPM. *
* *
* revision date changes *
* -------------------------------------------------------------------------- *
* 1.00 15.02.2002 created *
* 1.01 15.02.2002 release outputs with BASP *
* 3.00 03.06.2002 new structure of DPRAM. Needs firmware *
* Bb000124.3xx in the master! *
******************************************************************************/
#define VERSION "V300"
#include <conio.h>
#include <stdio.h>
#include <dos.h>
#define BYTE unsigned char
#define WORD unsigned short
//The Dual Port-RAM of the master is addressed from the PC with SEGMENT:OFFSET
//The Dos.h of the Borland C Compiler 4.5 shows e.g. the following definition:
//#define MK_FP(seg,ofs) ((void __seg *)(seg) + (void __near *)(ofs))
///////////////Location of the DP master in the address range of the PC/////////////////////
#define ADR_DPMASTER_SEG 0xC800 //basic-segment address of Dual Port Ram
////////////////////////////////////////////////////////////////////////////////////////////
#define PC_CPU_486_DPM
/////////////////////////////////////////////////////////////////////////////////////////
//
// The DPRAM between CPU and DP master is a 8k memory.
// Every cell of this area may be accessed with R e a d / W r i t e .
// The access has a data width of 8 B i t (= 1Byte).
//
// The DP master notices an 8k area.
// The LED- and VBUS- registers are only visible for the DP master.
// The areas 'PG channel' and 'page frame' may not be accessed
// because they are reserved for other devices!
// The PC notices an 8k area.
//
#define ADR_IM208_FPGA_BASE 0x0uL
#define ADR_IM208_IN (ADR_IM208_FPG 0x0400uL)
#define ADR_IM208_OUT (ADR_IM208_FPG 0x0800uL)
#define ADR_IM208_IN_BLOCKVERWALTUNG (ADR_IM208_FPG 0x0C00uL)
#define ADR_IM208_OUT_BLOCKVERWALTUNG (ADR_IM208_FPG 0x1000uL)
Establishing a
communication
C-program