ViewSonic VX800-3, Service Manual

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(2) TMDS Differential Input Clock (RC+ and RC-)
(3) Video Clock (VCLK) input pin
(4) Host Interface Transfer Clock (HCLK for 6-Wire nibble; SCL for 2-wire serial)
The gm5120 has an Input Format Measurement block (the IFM) providing the capability
of measuring the horizontal and vertical timing parameters of the input video source. This
information may be used to determine the video format and to detect a change in the input
format. It is also capable of detecting the field type of interlaced formats.
The IFM features a host programmable reset, separate from the regular gm5120 soft
reset. This reset disables the IFM, reducing power consumption. The IFM is capable of
operating while gm5120 is running in power down mode.
Horizontal measurements are measured in terms of the selected IFM_CLK (either
T_CLK or R_CLK/4), while vertical measurements are measured in terms of HSYNC
pulses.
The gm5120 OSD controller supports both character-mapped and bitmapped modes. A
user programmable palette of 256 true colors (255 colors, + 1 transparent) is available. In
character mapped mode, a maximum of four colors per character are available. In 8-bit
bitmapped mode, any pixel can be assigned any one of 256 user-defined true colors. In
4-bit bitmapped mode, any pixel can be assigned any one of 16 user-defined true colors (15
colors plus one transparent).
The gm5120 incorporates an embedded microprocessor, or OCM (On-Chip
Microprocessor).This processor is intended to simplify the gm5120 system software
implementation by providing embedded macro functions such as OSD menu configurations.
It is not intended to replace the system microprocessor.
An arbitration mechanism handles the register access requests from the OCM and the
system. micro.
1.4 LVDS Transmitter
IC500, 501 (SN75LVDS83) FlatLink transmitters contains four 7-bit parallel-load
serial-out shift registers, a ҏ c lock synthesizer, and five low-voltage differential-signaling
(LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of
single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted over five
balanced-pair conductors for receipt by a compatible receiver,
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