ViewSonic VX800-3, Service Manual

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When transmitting, data bits D0 through D27 are each loaded into registers upon the edge
of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected by way
of the clock select (CLKSEL) terminal. The frequency of CLKIN is multiplied seven times ( ) and
then used to unload the data registers in 7-bit slices and serially. The four serial streams and a
phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of
CLKOUT is the same as the input clock, CLKIN.
The SN75LVDS83 requires no external components and little or no control. The data bus
appears the same at the input to the transmitter and output of the receiver with the data
transmission transparent to the user. The only user intervention is the possible use of the
shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS output
drivers for lower power consumption. A low-level signal on SHTDN clears all internal registers
to a low level.
4 6 !
ViewSonic Corporation
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VX 8 00-3