UG:309
Page 12
The ENA_POL and KBIT2 registers are single bit registers. A “0” in the ENA_POL register is the default
value. This means the PI33xx‑xx will enable when the ENA pin is floating or logic high. Pulling down
ENA pin will disable the PI33xx‑xx. If a “1” is programmed into the ENA_POL register, the ENA polarity
reverses. If the ENA pin is floating or logic low, the PI33xx‑xx is enabled. Pulling the ENA pin high will
disable the PI33xx‑xx.
The KBIT2 register may only be written with a “1” entered into the dialog box. This register can not be
read, it is write only. Burning this register will prevent making any more changes to any register, even if
there are unused bits available to burn.
Start of T1 (ZVS)
Turn on of high side
MOSFET
External sync pulse
falling edge
Start of T1 (ZVS)
Turn on of high side
MOSFET
External sync pulse
falling edge
Figure 13
PI33xx‑xx ZVS buck sync to
T1 timing relationship
where VS = Ch3 VS1
SYN[3:0]
SYN[3]
SYN[2:0]
Polarity Bit
Control Bits
SYNC Delay
0 = Falling
000
NONE
1 = Rising
001
3/4MP
100
2/3MP
101
1/2MP
110
1/3MP
111
1/4MP
Summary of Contents for PI33 EVAL1 Series
Page 13: ...UG 309 Page 13 Figure 14 PI33xx xx SYNC 1000 timing Figure 15 PI33xx xx SYNC 1111 1 4MP ...
Page 14: ...UG 309 Page 14 Figure 16 PI33xx xx SYNC 1110 1 3MP Figure 17 PI33xx xx SYNC 1101 1 2MP ...
Page 15: ...UG 309 Page 15 Figure 18 PI33xx xx SYNC 1100 2 3MP Figure 19 PI33xx xx SYNC 1001 3 4MP ...