UG:309
Page 11
To understand the relationship between the synchronization timing and the PI33xx‑xx operation, an
overview of the PI33xx‑xx power train timing is shown in Figure 12. There are three main timing states
in the ZVS buck topology, T1, T3 and T4 as defined below:
T1:
T1 defines the start of a power cycle when the clamp switch has opened and the zero voltage
switching resonant action has started, followed by the turn on of Q1 and continuing until Q1 turns off.
During T1, current ramps up to a positive peak value, charge is delivered to the output capacitor and
energy is stored in the output inductor.
T3:
Q1 has turned off, Q2 has turned on and energy stored in the inductor is delivered to the load. As
the current in the inductor passes through zero, energy is stored in the inductor to provide zero‑voltage
switching for the next time Q1 is required to turn on.
T4:
After Q2 turns off, the clamp switch turns on to preserve the energy stored in the inductor to be
used for the next T1, while clamping VS to V
OUT
. At the end of T4 and beginning of T1, the clamp
switch opens and the parasitic capacitance of Q1 and Q2 resonates with the output inductor to provide
zero‑voltage switching.
The rising edge of SYNCO defines the beginning of T1 and can be observed in Figure 13. The rising
edge of SYNCO is synchronized to SYNCI rising or falling edge as programmed plus any delay desired.
Figure 13 shows the timing relationship of SYNCO, SYNCI and the phase node VS with default timing
and phase delay. Note that the node VS in the schematic of Figure 12 is called VS1 in Figure 13 and can
be observed on Channel 3 of the plot.
= Clamp open
Q1
Q2
Cin
VS
LS
Driver
HS
Driver
ZVS-Buck
Vin
Clamp
Switch
Q1
Q2
Cin
VS
LS
Driver
HS
Driver
ZVS-Buck
Vin
Clamp
Switch
Q1
Q2
Cin
VS
LS
Driver
HS
Driver
ZVS-Buck
Vin
Clamp
Switch
Sync at T1
T1
T3
T4
Q1
Q2
CLAMP
SWITCH
VS
ON
ON
ON
ON
ON
ON
I_L
IQ1
= Clamp open
= Clamp open
Q1
Q2
Cin
VS
LS
Driver
HS
Driver
ZVS-Buck
Vin
Clamp
Switch
Q1
Q2
Cin
VS
LS
Driver
HS
Driver
ZVS-Buck
Vin
Clamp
Switch
Q1
Q2
Cin
VS
LS
Driver
HS
Driver
ZVS-Buck
Vin
Clamp
Switch
Q1
Q2
Cin
VS
LS
Driver
HS
Driver
ZVS-Buck
Vin
Clamp
Switch
Q1
Q2
Cin
VS
LS
Driver
HS
Driver
ZVS-Buck
Vin
Clamp
Switch
V
OUT
Q1
Q2
Cin
C
OUT
VS
LS
Driver
HS
Driver
ZVS-Buck
Vin
Clamp
Switch
Sync at T1
T1
T3
T4
Q1
Q2
CLAMP
SWITCH
VS
ON
ON
ON
ON
ON
ON
I_L
IQ1
T1
T3
T4
Q1
Q2
CLAMP
SWITCH
VS
V
OUT
V
IN
ON
ON
ON
ON
ON
ON
I_L
IQ1
I
OUT
C
OUT
C
OUT
V
OUT
V
OUT
Figure 12
ZVS buck topology
timing diagram
Summary of Contents for PI33 EVAL1 Series
Page 13: ...UG 309 Page 13 Figure 14 PI33xx xx SYNC 1000 timing Figure 15 PI33xx xx SYNC 1111 1 4MP ...
Page 14: ...UG 309 Page 14 Figure 16 PI33xx xx SYNC 1110 1 3MP Figure 17 PI33xx xx SYNC 1101 1 2MP ...
Page 15: ...UG 309 Page 15 Figure 18 PI33xx xx SYNC 1100 2 3MP Figure 19 PI33xx xx SYNC 1001 3 4MP ...
