UG:309
Page 3
Figure 2
PI33xx‑xx block diagram
showing I
2
C hardware interface
Addressing & Register Mapping
Figure 2 shows the PI33xx‑xx I
2
C™ hardware interface. The PI33xx‑xx supports floating addressing so
that two address lines allows for up to eight programmable addresses. The address is 7 bit with the
read/write bit not included. Table 1 shows the address range that can be achieved using all possible
combinations of ADR0 and ADR1. Bits A[6] – A[3] are fixed internally and may not be changed.
The least significant 3 bits; A[2] – A[0], will assume the values in the table based on the decoding of
ADR1 and ADR0. A zero or one indicates the logic strength of the bit and “NC” indicates that the pin
is floating or not connected. The HEX column indicates the final address in hexadecimal, while the DEC
column is the decimal address value.
Table 1
Addressing options
(See Table 3 where
V
CC
= PI33xx‑xx fixed,
internal 5.1V bias rail)
PGND
SGN
D
SYNCO
PGD
Q1
Q2
ADR
0
SDA
V
CC
ADR
1
EN
SYNCI
TRK
EAO
ADJ
VS1
Power
Control
Interface
Memory
+
–
VOUT
REM
SCL
R4
R2
R3
V
OUT
0Ω
R1
ZVS Control
1V
VIN
I
2
C Hardware Interface Signals
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
R/W
ADR1
ADR0
HEX
DEC
1
0
0
1
0
0
0
X
0
0
48
72
1
0
0
1
0
0
1
X
0
NC
49
73
1
0
0
1
0
1
0
X
0
1
4A
74
1
0
0
1
0
1
1
X
NC
0
4B
75
1
0
0
1
1
0
0
X
NC
NC
4C
76
1
0
0
1
1
0
1
X
NC
1
4D
77
1
0
0
1
1
1
0
X
1
0
4E
78
1
0
0
1
1
1
1
X
1
1 or NC
4F
79
Summary of Contents for PI33 EVAL1 Series
Page 13: ...UG 309 Page 13 Figure 14 PI33xx xx SYNC 1000 timing Figure 15 PI33xx xx SYNC 1111 1 4MP ...
Page 14: ...UG 309 Page 14 Figure 16 PI33xx xx SYNC 1110 1 3MP Figure 17 PI33xx xx SYNC 1101 1 2MP ...
Page 15: ...UG 309 Page 15 Figure 18 PI33xx xx SYNC 1100 2 3MP Figure 19 PI33xx xx SYNC 1001 3 4MP ...
