UG:121
Page 13
General Shut Down/GSD (CBJ3-10)
The GSD control pin on CBJ3-10 allows simultaneous shut down of all outputs. This pin must be pulled
down to less than 0.7V, and will typically source 250mA (1mA maximum) to shut down all outputs. The
GSD pin should be open circuited or driven high to a logic-high voltage of 3.5V or greater when not in
use, or when the outputs are to be enabled. Do not apply more than 5V to this input.
AC OK (CBJ3-3)
AC OK is an active high TTL compatible signal and provides a status indication of the AC input power.
It is on pin CBJ3-3 and is capable of sinking 5mA maximum. This signal switches to a TTL "1" when the
high-voltage bus exceeds low-line condition during turn-on. Upon loss of input power, the bus voltage
will drop, causing the AC OK signal to go low. Typically, a 3ms holdup time is provided for a 500W load
following the loss of the AC OK signal.
Auxiliary V
CC
+5V/40mA (CBJ3-12)
The V
CC
on CBJ3-12 is an auxiliary 5V regulated power source. It is +5V
DC
±5% with respect to signal
ground and can supply 40mA maximum. It is capable of withstanding a short, but shorted user
interface functionality will be lost.
Power Good Read (PGR, CBJ3-2)
This pin initiates the Power Good Read sequence. A logic-high applied to this pin will cause the power
supply to enter the Power Good Read status mode. In this mode, the I/O lines (CBJ3-4 to CBJ3-9) will be
outputs. These outputs give an indication of the status of the modules of the power supply. A high on
an I/O line (CBJ3-4 to CBJ3-9) indicates a module is ON and functioning and a low indicate the module
is OFF or in a fault condition. The Power Good status data will be valid on the ED lines
(CBJ3-4 to CBJ3-9) when the Power Good Data Valid (PGDV) pin (CBJ3-11) asserts a logic-high. Applying
a logic-low or opening the PGR pin puts the power supply back in the enable/disable mode. Instructions
for using this function are on page 11 under module Power Good status mode.
Power Good Data Valid (PGDV- CBJ3-11)
Upon entering the Power Good Read status mode (PGR=1, CBJ3-2), the data will not be valid on the
I/O lines (CBJ3-4 to CBJ3-9) until the PGDV pin asserts itself logic-high. This pin can source up to 5mA.
When this pin is logic-low, Power Good status data is not valid or the power supply is not in the Power
Good Read status mode.
Figure 6
Auxiliary V
CC
78M05
Auxiliary V
CC
CBJ3-12
0.1µF
Signal Ground
CBJ3
CBJ3-1
+5V/40mA