VIA EPIA-P910 User Manual
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2.2.4.
KB/MS/LPC/GPIO/SMBus Combination Pin Header
The VIA EPIA-P910 includes one KB, MS, LPC, GPIO, and SMBus combination pin header block labeled as
“CN1”. The combination pin header is for connecting KB, MS, LPC, GPIO, and SMBus devices. The pinouts
of the pin header are shown below.
Figure 12: KB/MS/LPC/GPIO/ SMBus combination pin header diagram
Pin
Signal
Pin
Signal
1
LAD3
2
GND
3
LAD2
4
SIO_CLK1
5
LAD1
6
PCICLK3
7
-LFRAME
8
-LDRQ0
9
LAD0
10 SERIRQ
11 -PCIRST
12 GND
13 3.3V
14 3.3V
15 +3.3V
16 +5V
17 -LID/GPI7
18 -INTB/GPIO8
19 -THRM/GPI9
20 -INTC/GPIO9
21 -EXTSMI/GPI5
22 GPIO12/GPIO12
23 -BATLOW/GPI4
24 GPIO32/GPIO32
25 GND
26 +5VSUS
27 KBDT
28 KBCK
29 MSDT
30 MSCK
Table 11: KB/MS/LPC/GPIO/SMBus combination pin header pinouts