VESTEL 17MB15E-5, Service Manual

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15.19. SDA55XX (SDA5550)
15.19.1.
General description
The SDA55XX is a single chip teletext decoder for decoding World System Teletext data as well as Video
Programming System (VPS), Program Delivery Control (PDC), and Wide Screen Signalling (WSS) data used for
PAL plus transmissions (Line 23). The device also supports Closed caption acquisition and decoding. The
device provides an integrated general-purpose, fully 8051-compatible Microcontroller with television specific
hardware features. Microcontroller has been enhanced to provide powerful features such as memory banking,
data pointers, and additional interrupts etc. The on-chip display unit for displaying Level 1.5 teletext data can
also be used for customer defined on screen displays. Internal XRAM consists of up to16 Kbytes. Device has an
internal ROM of up to 128 KBytes. ROMless versions can access up to 1 MByte of external RAM and ROM. The
SDA 55XX supports a wide range of standards including PAL, NTSC and contains a digital slicer for VPS, WSS,
PDC, TTX and Closed Caption, an accelerating acquisition hardware module, a display generator for Level 1.5
TTX data and powerful On screen Display capabilities based on parallel attributes, and Pixel oriented characters
(DRCS).
The 8-bit Microcontroller runs at 360 ns. cycle time (min.). Controller with dedicated hardware does most of the
internal TTX acquisition processing, transfers data to/from external memory interface and receives/ transmits
data via I
2
C-firmware user-interface. The slicer combined with dedicated hardware stores TTX data in a VBI
buffer of 1 Kilobyte. The Microcontroller firmware performs all the acquisition tasks (hamming and parity-checks,
page search and evaluation of header control bits) once per field. Additionally, the firmware can provide high-
end Teletext features like Packet-26-handling, FLOF, TOP and list-pages. The interface to user software is
optimized for minimal overhead. SDA 55XX is realized in 0.25 micron technology with 2.5 V supply voltage and
3.3 V I/O (TTL compatible). The software and hardware development environment (TEAM) is available to
simplify and speed up the development of the software and On Screen Display. TEAM stands for TVT Expert
Application Maker. It improves the TV controller software quality in following aspects:
– Shorter time to market
– Re-usability
– Target independent development
– Verification and validation before targeting
– General test concept
– Graphical interface design requiring minimum programming and controller know how.
– Modular and open tool chain, configurable by customer.
15.20. Sil 9993
15.20.1.
General Description
The SiI 9993 is the first generation of PanelLink receivers that are designed for the HDMI 1.0 (High Definition Multimedia
Interface) specification. DTVs, plasma displays, LCD TVs and projectors can now provide the purest level of protected
digital audio/video over a simple, low cost cable. Backwards compatibility with DVI 1.0 allows HDMI systems to connect
to any DVI 1.0 host (DVD players, HD set top boxes, D-VHS players and receivers, PC). The SiI 9993 incorporates a
flexible audio and video interface. The receiver can connect to RGB input and output YCbCr using an integrated color
space converter. This allows full backward compatibility to DVI, and interfaces to all major video processors. A S/PDIF
port can output PCM encoded data as well as Dolby Digital, DTS and all other formats capable of being sent over S/PDIF.
A 2-channel I2S port outputs data converted from S/PDIF. The SiI 9993 comes pre-programmed with HDCP keys, greatly
simplifying the manufacturing process, lowering costs, all the while providing the highest level of HDCP key security.
Silicon Image’s PanelLink receivers use the latest generation of PanelLink TMDS core technology. These PanelLink cores
pass all HDMI compliancy tests.
15.20.2.
Features
• HDMI 1.0 and DVI 1.0 compliant receiver
• Integrated PanelLink core supports DTV resolutions (480i/576i/480p/576p/720p/1080i)
• Digital video interface supports video processors:
o 24-bit RGB 4:4:4
o 24-bit YCbCr 4:4:4
o 16/20/24-bit YCbCr 4:2:2
o 8/10/12-bit YCbCr 4:2:2 embedded syncs
• Analog RGB and YPbPr output:
o 10-bit DAC
o Separate or Composite Syncs (Sync on G)