VESTEL 17MB15E-5, Service Manual

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- 2.5 ns Maximum from Clock Input to Data Output
- UltraMOS® Advanced CMOS Technology
• 3.3V LOW VOLTAGE 16V8 ARCHITECTURE
- JEDEC-Compatible 3.3V Interface Standard
- 5V Compatible Inputs
- I/O Interfaces with Standard 5V TTL Devices (GAL16LV8C)
• ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only)
• E2 CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
- 100% Tested/100% Yields
- High Speed Electrical Erasure (<100ms)
- 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
- 100% Functional Testability
• APPLICATIONS INCLUDE:
- Glue Logic for 3.3V Systems
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS
15.6.3.
Pin connections
15.7.
15.8. K6R4008V1D
15.8.1.
Description
The K6R4008V1D is a 4,194,304-bit high-speed Static Random Access Memory organized as 524,288 words by
8 bits. TheK6R4008V1D uses 8 common input and output lines and has an output enable pin which operates
faster than address access time at read cycle. The device is fabricated using SAMSUNG
′ s advanced CMOS
process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-
speed system applications. The K6R4008V1D is packaged in a 400 mil 36-pin plastic SOJ and 44-pin plastic
TSOP type II.
15.8.2.
Features
• Fast Access Time 8, 10ns(Max.)
• Low Power Dissipation
- Standby (TTL) : 20mA(Max.)
(CMOS) : 5mA(Max.)
- Operating K6R4008V1D-08 : 80mA(Max.)