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14
15.2.4.
PIN Function Table
PIN DESCRIPTIONS
A0, A1, A2 Chip Address Inputs
The A0...A2 inputs are used by the 24C32 for multiple device operation and conform to the two-wire bus stan-
dard. The levels applied to these pins define the address block occupied by the device in the address map. A
particular device is selected by transmitting the corresponding bits (A2, A1, and A0) in the control byte.
SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain
terminal; therefore the SDA bus requires a pull-up resistor to VCC (typical 10KQ for 100 kHz, 1KQ for 400 kHz).
For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved
for indicating the START and STOP conditions.
SCL Serial Clock
This input is used to synchronize the data transfer from and to the device.
15.3. 74LVC14A
15.3.1.
Description
The 74LVC14A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced
CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5V devices. This feature allows the use of
these devices as translators in a mixed 3.3 and 5V environment. The 74LVC14A provides six inverting buffers with
Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output
signals.
15.3.2.
Features
•
Wide supply voltage range from 1.2 to 3.6 V
•
CMOS low power consumption
•
Direct interface with TTL levels
•
Inputs accept voltages up to 5.5 V
•
Complies with JEDEC standard no.8-1A
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000V
MM EIA/JESD22-A115-A exceeds 200V.
•
Specified from -40 to +85C and -40 to +125C.
15.3.3.
Pinning
Summary of Contents for 17MB15E-5
Page 1: ...i 42 PLASMA TV 17MB15E 5 SERVICE MANUAL ...
Page 38: ...33 15 27 3 Pinning ...
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Page 62: ...57 18 APPENDIX A 18 1 EXPLODED VIEW AND PART LIST ...
Page 64: ...59 19 2 16 ELECTRICALDIAGRAMS 19 2 1 POWER BOARD ...
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Page 80: ...73 19 4 PRINT_LAY OUTS 19 4 1 Complete_PCB_Pattern_Schematic ...
Page 81: ...74 19 4 3 In 1_Ground_Level_PCB_Pattern ...
Page 82: ...75 19 4 4 In2_Power_Level_PCB_Patter ...
Page 83: ...76 19 4 5 Bottom_ Level_ PCB_ Pattern ...
Page 84: ...77 19 4 6 Top_Layer_Silk_Print ...
Page 85: ...78 19 4 7 Bottom_Layer_Silk_Print ...
Page 86: ...79 19 4 8 Topmask lgx ...
Page 87: ......
Page 88: ...81 19 4 10 17fav15 2pcb ...
Page 89: ...82 19 4 11 18amp05 2 pcb ...