Interfaces and Connectors
EBX-37 Reference Manual
28
LVDS
F
LAT
P
ANEL
D
ISPLAY
C
ONNECTOR
(J31,
J33)
The integrated LVDS Flat Panel Display in the VL-EBX-37 is an ANSI/TIA/EIA-644-1995
specification-compliant interface. VL-EBX-37 Models S and E have one LVDS connector at J31
and supports single-channel mode operation. Models A and F have an additional LVDS
connector at J33 to provide a second channel for optional dual-channel mode (both connectors
used concurrently to drive one LVDS display). Single-channel mode supports up to 24 bits of
RGB pixel data plus 4 bits of timing control on the four differential data output pairs. Dual-
channel mode supports up to 48 bits of RGB pixel data plus 4 bits of timing control on the eight
differential data output pairs. The second LVDS connector (J33) can not be used to support a
second LVDS panel. The LVDS clock frequency ranges from 25 MHz to 112 MHz.
CMOS Setup provides several options for standard LVDS flat panel types. If these options do not
match the requirements of the panel you are attempting to use, contact
for a custom video BIOS.
Table 7: LVDS Flat Panel Display Pinouts
J31
Pin
J31
Signal Name
J31
Function
J33
Pin
J33
Signal Name
J33
Function
1
GND
Ground
1
GND
Ground
2
NC
Not Connected
2
NC
Not Connected
3
LVDSA3
Diff. Data 3 (+)
3
LVDSB3
Diff. Data 3 (+)
4
LVDSA3#
Diff. Data 3 (
-
)
4
LVDSB3#
Diff. Data 3 (
-
)
5
GND
Ground
5
GND
Ground
6
LVDSCLK0
Differential Clock (+)
6
LVDSCLK1
Differential Clock (+)
7
LVDSCLK0# Differential Clock (
-
)
7
LVDSCLK1# Differential Clock (
-
)
8
GND
Ground
8
GND
Ground
9
LVDSA2
Diff. Data 2 (+)
9
LVDSB2
Diff. Data 2 (+)
10
LVDSA2#
Diff. Data 2 (
-
)
10
LVDSB2#
Diff. Data 2 (
-
)
11
GND
Ground
11
GND
Ground
12
LVDSA1
Diff. Data 1 (+)
12
LVDSB1
Diff. Data 1 (+)
13
LVDSA1#
Diff. Data 1 (
-
)
13
LVDSB1#
Diff. Data 1 (
-
)
14
GND
Ground
14
GND
Ground
15
LVDSA0
Diff. Data 0 (+)
15
LVDSB0
Diff. Data 0 (+)
16
LVDSA0#
Diff. Data 0 (
-
)
16
LVDSB0#
Diff. Data 0 (
-
)
17
GND
Ground
17
GND
Ground
18
GND
Ground
18
GND
Ground
19
+3.3V
+3.3V (Protected)
19
+5V
+5V
20
+3.3V
+3.3V (Protected)
20
+5V
+5V
Warning!
The power voltage supplied by the J33 connector is +5V. Plugging a 3.3V LVDS
panel into connector J33 could cause damage to the panel.
The power provided to pins 19 and 20 of both connectors is protected by a software-controllable
power switch (1 Amp max.). This switch is controlled by the L_VDD_EN signal from the LVDS
interface controller in the Intel GM45 controller. See the
Intel GM45 Datasheet
for detailed
information.
