VersaLogic Ocelot Reference Manual Download Page 25 | Manualshive

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Distributor of VersaLogic Corporation: Excellent Integrated System Limited

Datasheet of VL-CBR-2012 - 20" 24-BIT LVDS CABLE
Contact us: [email protected] Website: www.integrated-circuit.com

Physical Details

VL-EPMs-21 Reference Manual

18

Jumper Blocks

J

UMPERS

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HIPPED

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ONFIGURATION

Figure 10. Jumper Block Locations

V1

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1

3

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Summary of Contents for Ocelot

Page 1: ...cellent Integrated System Limited Stocking Distributor Stocking Distributor Click to view price real time Inventory Delivery Lifecycle Information Click to view price real time Inventory Delivery Life...

Page 2: ...d System Limited Datasheet of VL CBR 2012 20 24 BIT LVDS CABLE Contact us sales integrated circuit com Website www integrated circuit com Reference Manual DOC REV 4 3 2013 Ocelot VL EPMs 21 Intel Atom...

Page 3: ...ed Notice Although every effort has been made to ensure this document is error free VersaLogic makes no representations or warranties with respect to this product and specifically disclaims any implie...

Page 4: ...onal information and resources for this product including Reference Manual PDF format Operating system information and software drivers Data sheets and manufacturers links for chips used in this produ...

Page 5: ...tion and Setup 7 Initial Configuration 7 Basic Setup 7 CMOS Setup 10 Operating System Installation 10 Physical Details 11 Dimensions and Mounting 11 VL EPMs 21 Dimensions 11 VL CBR 5012 Dimensions 12...

Page 6: ...tors 26 SUMIT Connectors J1 J2 26 Ethernet Interface J3 28 Ethernet Connector 28 Ethernet Status LEDs 28 Video Interface J4 and J6 29 Display Control 29 Configuration 29 LVDS Flat Panel Display Connec...

Page 7: ...m Website www integrated circuit com Contents VL EPMs 21 Reference Manual vi I O Map 46 Interrupt Configuration 48 VersaLogic Registers 49 PLED and Product ID Register 49 Revision and Type Register 50...

Page 8: ...keyboard mouse and other devices on the VL CBR 5012 breakout board TVS devices for ESD protection Intel High Definition Audio HDA compatible SMSC hardware monitor Four RS 232 422 485 COM ports 460 Kb...

Page 9: ...mm connector Supports up to and including ATA 6 UDMA66 100 interface Supports two Parallel ATA IDE devices hard drive CD ROM CF etc Flash Storage 44 pin PATA Disk on Module Shares IDE channel master o...

Page 10: ...t Integrated System Limited Datasheet of VL CBR 2012 20 24 BIT LVDS CABLE Contact us sales integrated circuit com Website www integrated circuit com Introduction VL EPMs 21 Reference Manual 3 VL EPMs...

Page 11: ...ISCHARGE Warning Electrostatic discharge ESD can damage circuit boards disk drives and other components The circuit board must only be handled at an ESD workstation If an approved station is not avail...

Page 12: ...ndling resulting in CMOS resetting to factory defaults Technical Support If you are unable to solve a problem after reading this manual please visit the VL EPMs 21 product support web page below The s...

Page 13: ...gineer that can be contacted if any questions arise Quantity of items being returned The model and serial number barcode of each item A detailed description of the problem Steps you have taken to reso...

Page 14: ...DE data cable VL CBR 4405 IDE adapter board if you are using drives with 40 pin connectors VL CBR 1008 Power adapter cable You will also need an operating system OS installation CD ROM Basic Setup The...

Page 15: ...ug the breakout board VL CBR 5012 into socket J7 Plug a USB keyboard and USB mouse into socket J1 of the breakout board Note In DOS input is through a keyboard only Due to a limitation of the BIOS mou...

Page 16: ...oriented correctly and that adequate power will be supplied to the VL EPMs 21 and peripheral devices 5 Power On Turn on the ATX power supply and the video monitor If the system is correctly configure...

Page 17: ...d with the VL EPMs 21 is 6 5 101 Be sure to update the BIOS to the latest available revision from the VL EPMs 21 support page before installing the VL EPMs U1 Operating System Installation The standar...

Page 18: ...Details Dimensions and Mounting VL EPMS 21 DIMENSIONS The VL EPMs 21 complies with PC 104 Express dimensional standards Dimensions are given below to help with pre production planning and layout Figur...

Page 19: ...circuit com Physical Details VL EPMs 21 Reference Manual 12 Figure 4 VL EPMs21 Height Dimensions Not to scale All dimensions in inches Note Pass through PC 104 ISA connectors are included only on a an...

Page 20: ...can be stacked PC 104 only ISA modules must not be positioned between the VL EPMs 21 and any SUMIT modules on the stack The entire assembly can sit on a table top or be secured to a base plate When bo...

Page 21: ...e www integrated circuit com Physical Details VL EPMs 21 Reference Manual 14 External Connectors VL EPMS 21 CONNECTOR LOCATIONS TOP Figure 7 Connector Locations Top Pin 1 J1 SUMIT B 2 1 10 9 J2 SUMIT...

Page 22: ...ed Datasheet of VL CBR 2012 20 24 BIT LVDS CABLE Contact us sales integrated circuit com Website www integrated circuit com Physical Details VL EPMs 21 Reference Manual 15 VL EPMS 21 CONNECTOR LOCATIO...

Page 23: ...292 29 J5 IDE HD CD ROM or DOM FCI 89947 144LF VL CBR 44062 1 44 pin 2 mm latching two 44 pin 2 mm 3 221 2 288 33 J6 LVDS3 Molex 51146 2000 housing Molex 50641 8041 pins VL CBR 2012 or VL CBR 2010 or...

Page 24: ...Description J1 USB0 USB1 USB Type A USB Host J2 COM1 COM2 Kycon K42 E9P P A4N Dual DB 9 male J3 Audio In Out 3 5 mm dual audio jack J4 High Density Connector FCI 98414 F06 50ULF 2 mm 50 pin keyed head...

Page 25: ...et of VL CBR 2012 20 24 BIT LVDS CABLE Contact us sales integrated circuit com Website www integrated circuit com Physical Details VL EPMs 21 Reference Manual 18 Jumper Blocks JUMPERS AS SHIPPED CONFI...

Page 26: ...stor across COM2 RS 485 TXRX TXRX or RS 422 RX RX differential pair Out Rev 1 02 and later In Rev 1 01 and earlier 36 V1 5 6 COM3 Rx End point Termination In 120 Ohm termination active Out No terminat...

Page 27: ...5 VDC and all ground pins to prevent excess voltage drop The power connector is not fuse or diode protected Proper polarity must be followed or damage will occur Some manufacturers include a pin 1 ind...

Page 28: ...s watchdog timer is enabled by default during the power on self test POST pre boot sequence With the POST Watchdog parameter enabled in CMOS Setup a hang condition during POST will cause the watchdog...

Page 29: ...FACTORY DEFAULTS You can remove the V2 3 4 jumper to reset CMOS to factory defaults When resetting CMOS 1 Power off the VL EPMs 21 2 Remove the V2 3 4 jumper and power up the computer 3 Move the jumpe...

Page 30: ...level input or pushbutton or relay attached to the pushbutton interface Power consumption in standby mode is approximately 1 watt Wakeup typically occurs in 1 to 6 seconds Standby mode functionality...

Page 31: ...BOOL SetSystemPowerState BOOL fSuspend BOOL fForce Parameters fSuspend in If this parameter is TRUE the system is suspended If the parameter is FALSE the system hibernates This parameter is ignored in...

Page 32: ...er Cycle 3 sec off time e 0x1D3 30h Power Off 2 Configure Super I O WDT GP60 pin 0x0C47 7 3 0 Examples a 0x0C47 POR default 0Eh b 0x0C47 0Eh WDT enable Push Pull Inverted 3 Configure Timescale 0x0C65...

Page 33: ...ter in slave out 11 USB_OC USB overcurrent flag 12 SPI uWire_DI SPI master out slave in 13 Reserved Reserved 14 SPI uWire_CLK SPI clock 15 5V 5V power 16 SPI uWire_CS0 SPI slave select 5 17 USB7 USB7...

Page 34: ...ock 4 11 C_CLKn Link C clock 5 12 B_CLKn Link B clock 4 13 CPRSNT GND Link C present 14 GND Ground 15 C_PETp5 Link C lane 5 transmit 16 C_PERp5 Link C lane 5 receive 17 C_PETn5 Link C lane 5 transmit...

Page 35: ...VS components to help protect against ESD damage Table 7 RJ45 Ethernet Connector Pinout Fast Ethernet Gigabit Ethernet J3 Pin Signal Name Function Signal Name Function 1 T Transmit Data MID0 Media Dep...

Page 36: ...or without a video card attached headless DISPLAY CONTROL Pin Signal Name Function 1 VEN Backlight inverter power enable 2 GMbus_CLK I2C based backlight brightness control clock 3 GND Ground 4 GMbus_D...

Page 37: ...ferential data output pairs The LVDS clock frequency ranges from 25 MHz to 112 MHz The 3 3V power provided to pins 19 and 20 of J6 is protected by a 1 amp fuse See the Connector Location Diagram on pa...

Page 38: ...084SN01 8 4 800 x 600 18 bit LVDS TFT eVision Displays xxx104S01 series 10 4 800 x 600 18 bit LVDS TFT au Optronix B104SN01 10 4 800 x 600 18 bit LVDS TFT Sharp LQ121S1LG411 12 1 800 x 600 18 bit LVDS...

Page 39: ...o be redirected to COM1 unless a signal a Ctrl C character is detected from the terminal Console redirection can also be set to Always or Never You can direct console output to any COM port Notes on c...

Page 40: ...n Module DOM flash storage devices in capacities from 1 to 8 GB that attach to the IDE connector The VL F20 series of DOMs have a 44 pin 2 mm connector and are secured to the board with one M2 5 x 6mm...

Page 41: ...DEVICE VersaLogic recommends that you load operating systems or other software onto a DOM device via a USB drive or through the Ethernet interface Warning If you attach a DOM to an IDE cable be caref...

Page 42: ...1 power 5V isolated 2 J2 Top Receive Data 30 J1 Bottom Data 3 Clear to Send 31 Data 4 Ground 32 Ground 5 Transmit Data 33 USB2 USB Client Detect Input 6 Request to Send 34 J7 Data 7 COM2 Ground 35 Dat...

Page 43: ...independently enabled or disabled Note It is possible to create a resource conflict if a COM port is enabled in CMOS and its I O address space is consumed by an LPC based SUMIT module or forwarded to...

Page 44: ...to pins 4 6 2 RXD Receive Data 3 TXD Transmit Data 4 DTR Shorted to pins 1 6 5 GND Ground 6 DSR Shorted to pins 1 4 7 RTS Request to Send 8 CTS Clear to Send 9 RI Not connected J2 Bottom DB 9 Pin Sign...

Page 45: ...ion Programmable LED Connector J7 includes an output signal for a programmable LED Connect the cathode of the LED to J7 pin 37 connect the anode to 5V A 300 on board resistor limits the current to 15...

Page 46: ...nux operating systems To obtain the most current versions consult the VL EPMs 21 product support page The J7 main I O connector provides the line level stereo input and line level stereo output connec...

Page 47: ...he onboard CPLD containing the PC 104 bridge VersaLogic registers and the SPI controller see the figure below Special care must be taken to avoid resource conflicts between all LPC bus based targets i...

Page 48: ...es The VL EPMs 21 does not support standard ISA memory cycles due to limitations of the Intel Atom architecture The VL EPMs 21 does provide a way to map up to 64 KB of ISA memory to the top of the boa...

Page 49: ...cted SPI is in its simplest form a three wire serial bus One signal is a Clock driven only by the permanent Master device on board The others are Data In and Data Out with respect to the Master The SP...

Page 50: ...e D5 D4 SPILEN SPI Frame Length Sets the SPI frame length This selection works in manual and auto slave select modes SPILEN1 SPILEN0 Frame Length 0 0 8 bit 0 1 16 bit 1 0 24 bit 1 1 32 bit D3 MAN_SS S...

Page 51: ...Enables or disables the use of the selected IRQ IRQSEL by an SPI device 0 SPI IRQ disabled default 1 SPI IRQ enabled Note When an IRQ is enabled for the SPX bus it has priority over the PC 104 bus Fo...

Page 52: ...3 contains the most significant byte MSB of the SPI data word A write to this register will initiate the SPI clock and if the MAN_SS bit 0 will also assert a slave select to begin an SPI bus transacti...

Page 53: ...es in the VL EPMs 21 I O map User I O devices should be added using care to avoid the devices already in the map as shown in the following table Table 20 On Board I O Devices I O Device Standard I O A...

Page 54: ...an of the VL EPMs 21 under test running DOS 6 22 This example is not necessarily an accurate description for the results under Windows Linux VxWorks or other operating systems Each system will be diff...

Page 55: ...terfaces and Connectors VL EPMs 21 Reference Manual 48 Interrupt Configuration Table 22 Interrupt Configuration default setting allowed setting Source IRQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Timer 0...

Page 56: ...7 D6 D5 D4 D3 D2 D1 D0 PLED PC6 PC5 PC4 PC3 PC2 PC1 PC0 Table 23 PLED and Product Code Register Bit Assignments Bit Mnemonic Description D7 PLED Light Emitting Diode Controls the programmable LED on c...

Page 57: ...D7 D3 PR PLD Revision Code These bits are hard coded and represent the CPLD revision PR4 PR3 PR2 PR1 PR0 Revision 0 0 0 0 1 Rev 0 23 and 0 24 0 0 0 1 0 Rev 0 31 and 1 00 0 0 0 1 1 Rev 1 00 These bits...

Page 58: ...D6 D5 D4 D3 D2 D1 D0 Reserved Reserved Reserved Reserved Reserved Reserved GPI_JMP CMOSRST Table 25 GPI Jumper Register Bit Assignments Bit Mnemonic Description D7 D2 Reserved These bits have no func...

Page 59: ...tchdog Timer Mode These bits set the behavior of the System Management Controller for the watchdog timer On detecting a watchdog timeout the System Mgt Controller can perform a system wide hardware re...

Page 60: ...ion PC104_BLK_EN0 Read Write 1D4h D7 D6 D5 D4 D3 D2 D1 D0 IOBLK_EN7 IOBLK_EN6 IOBLK_EN5 IOBLK_EN4 IOBLK_EN3 IOBLK_EN2 IOBLK_EN1 IOBLK_EN0 Table 27 PC 104 I O Block Enable Register 0 Bit Assignments Bi...

Page 61: ...LK_EN9 IOBLK_EN8 Table 28 PC 104 I O Block Enable Register 1 Bit Assignments Bit Mnemonic Description D7 D4 Reserved These bits have no function D3 IOBLK_EN11 PC 104 I O port range 0x400 0xAFF enable...

Page 62: ...ing system to other devices before enabling them for the PC 104 bus to avoid conflicts PC104_IRQ_EN0 Read Write 1DEh D7 D6 D5 D4 D3 D2 D1 D0 IRQ11_EN IRQ10_EN IRQ9_EN IRQ7_EN IRQ6_EN IRQ5_EN IRQ4_EN I...

Page 63: ...8 bit on PC 104 bus 1 16 bit I O cycles enabled on PC 104 bus D6 MEM_EN3 ISA Memory Access 16 KB ISA memory window 0x000DC000 to 0x000DFFFF forwarded to 0xFFD0C000 to 0xFFD0FFFF 0 disable on PC 104 b...

Page 64: ...it com Website www integrated circuit com VL EPMs 21 Reference Manual 57 Appendix A References PC Chipset Intel Atom Intel Atom Datasheet Ethernet Controller Intel 82574L Ethernet Controller Intel 825...

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