Special Control Register
Special Control Register
SCR (READ/WRITE) 00E0h (or 01E0h via CMOS Setup)
D7 D6 D5 D4 D3
D2
D1
D0
LED OVERTEMP GPI
GPO
HDOGNMI WDOGSTA WDOGNMI WDOGRST
Table 20: Special Control Register Bit Assignments
Bit Mnemonic Description
D7 LED
Light Emitting Diode — Controls the programmable LED connected to
JS4[27A/28A]
LED = 0
Turns LED off.
LED = 1
Turns LED on.
D6 OVERTEMP
Temperature Status — Indicates CPU case temperature.
TEMP = 0
CPU case temperature is below value set in CMOS Setup
TEMP = 1
CPU case temperature is above value set in CMOS Setup
Note! This bit is a read-only bit.
D5 GPI
General Purpose Input — Indicates the status of TTL input at JS3[38B].
GPI = 0
Logic High
GPI = 1
Logic Low
Note! This bit is a read-only bit.
D4 GPO
General Purpose Output — Controls TTL output at JS3[37B].
GPO = 0
Logic High
GPO = 1
Logic Low
D3 HDOGNMI
Non-Maskable Interrupt Enable — Controls the generation of Non-Maskable
Interrupts whenever the CPU temperature sensor detects an over-temperature
condition.
HDOGNMI = 0
Disable
HDOGNMI = 1
Enable
D2 WDOGSTA
WDOG STATUS — Indicates if the watchdog timer has expired.
WDOGSTA = 0 Timer has not expired.
WDOGSTA = 1 Timer has expired.
D1 WDOGNMI
Watch Dog Non-Maskable Interrupt Enable — Enables the generation of a
Non-maskable interrupt when the watchdog timer expires.
WDOGNMI = 0
Disables
WDOGNMI = 1
Enables
D0 WDOGRST
Watch Dog Reset Enable — Enables and disables the watchdog timer reset
circuit.
WDOGRST = 0 Disables the watchdog timer.
WDOGRST = 1 Enables the watchdog timer.
EPM-CPU-10 Reference Manual
Reference – 41