Parallel Port
Parallel Port
The
EPM-CPU-10
includes a standard bi-directional/EPP/ECP compatible LPT port which resides at
the PC standard address of 378h. The port can be enabled/disabled and interrupt assignments can
be made via the CMOS Setup screen. The pinout of the JA connector applies to use of the
VersaLogic transition cable #VL-CBL-8001.
This connector is protected with IEC 61000-4-2 (Level 4) rated TVS components to help protect
against ESD damage.
Table 9: LPT1 Parallel Port Pinout
JS4
Pin
Centronics
Signal
Signal
Direction
JA
Pin
1A Strobe
Out
1
2A Auto
feed
Out
14
3A
Data bit 1
In/Out
2
4A Printer
error
In
15
5A
Data bit 2
In/Out
3
6A Reset
Out
16
7A
Data bit 3
In/Out
4
8A Select
input
Out
17
9A
Data bit 4
In/Out
5
10A Ground
—
18
11A Data bit 5
In/Out
6
12A Ground
—
19
13A Data bit 6
In/Out
7
14A Ground
—
20
15A Data bit 7
In/Out
8
16A Ground
—
21
17A Data bit 8
In/Out
9
18A Ground
—
22
19A Acknowledge
In
10
20A Ground
—
23
21A Port
Busy
In
11
22A Ground
—
24
23A Paper
End
In
12
24A Ground
—
25
25A Select
In
13
EPM-CPU-10 Reference Manual
Reference – 27