VersaLogic EPM-CPU-10, Reference Manual, Page: 42 / 55

Video Interface
F
LAT
P
ANEL
D
ISPLAY
C
ONNECTOR
See the Connector Location Diagram on page 11 for pin and connector location information.
Table 15: Flat Panel Display Pinout
Pin
Signal
Name
Function Mono
SS
8-bit
Mono
DD
8-bit
Mono
DD
16-bit
Color
TFT
9-bit
12-bit
16-bit
Color
TFT
18-bit
24-bit
Color
TFT
36-bit
Color
TFT HR
18-bit
24-bit
Color
STN SS
8-bit
(4bP)
Color
STN SS
16-bit
(4bP)
Color
STN DD
8-bit
(4bP)
Color
STN DD
16-bit
(4bP)
Color
STN DD
24-bit
JN4[1] +12V Power Supply
JN4[2] +12V Power Supply
JN4[3] GND Ground
JN4[4] GND Ground
JN4[5] +5V Power Supply
JN4[6] +5V Power Supply
JN4[7] ENAVEE Power sequencing control
for LCD bias voltage
JN4[8] GND Ground
JN4[9] FP0 Data Output D0 UD3 UD7 B0 B0 FB0 FB0 R1 R1 UR1 UR0 UR0
JN4[10] FP1 “ “ D1 UD2 UD6 B1 B1 FB1 FB1 B1 G1 UG1 UG0 UG0
JN4[11] FP2 “ “ D2 UD1 UD5 B2 B2 FB2 FB2 G2 B1 UB1 UB0 UB0
JN4[12] FP3 “ “ D3 UD0 UD4 B3 B3 FB3 FB3 R3 R2 UR2 UR1 LR0
JN4[13] FP4 “ “ D4 LD3 UD3 B4 B4 FB4 SB0 B3 G2 LR1 LR0 LG0
JN4[14] FP5 “ “ D5 LD2 UD2 G0 B5 FB5 SB1 G4 B2 LG1 LG0 LB0
JN4[15] FP6 “ “ D6 LD1 UD1 G1 B6 SB0 SB2 R5 R3 LB1 LB0 UR1
JN4[16] FP7 “ “ D7 LD0 UD0 G2 B7 SB1 SB3 B5 G3 LR2 LR1 UG1
JN4[17] FP8 “ “ LD7 G3 G0 SB2 FG0 B3 UG1 UB1
JN4[18] FP9 “ “ LD6 G4 G1 SB3 FG1 R4 UB1 LR1
JN4[19] FP10 “ “ LD5 G5 G2 SB4 FG2 G4 UR2 LG1
JN4[20] FP11 “ “ LD4 R0 G3 SB5 FG3 B4 UG2 LB1
JN4[21] FP12 “ “ LD3 R1 G4 FG0 SG0 R5 LG1 UR2
JN4[22] FP13 “ “ LD2 R2 G5 FG1 SG1 G5 LB1 UG2
JN4[23] FP14 “ “ LD1 R3 G6 FG2 SG2 B5 LR2 UB2
JN4[24] FP15 “ “ LD0 R4 G7 FG3 SG3 R6 LG2 LR2
JN4[25] FP16 “ “ R0 FG4 FR0 LG2
JN4[26] FP17 “ “ R1 FG5 FR1 LB2
JN4[27] FP18 “ “ R2 SG0 FR2 UR3
JN4[28] FP19 “ “ R3 SG1 FR3 UG3
JN4[29] FP20 “ “ R4 SG2 SR0 UB3
JN4[30] FP21 “ “ R5 SG3 SR1 LR3
JN4[31] FP22 “ “ R6 SG4 SR2 LG3
JN4[32] FP23 “ “ R7 SG5 SR3 LB3
JN4[33] GND Ground
JN4[34] GND Ground
JN4[35] SHFCLK Shift Clock.
Pixel clock for flat panel data.
JN4[36] FLM First Line Marker.
Flat panel equivalent of VSYNC.
JN4[37] DE Display Enable or
M signal (ADCCLK) or BLANK#
JN4[38] LP Latch Pulse.
Flat panel equivalent of HSYNC.
JN4[39] GND Ground
JN4[40] ENABKL Enable Backlight. Can be
programmed for other functions.
JN4[41] DDCDATA Serial Data
JN4[42] DDCCLK Serial Data
JN4[43] +3V Power Supply
JN4[44] +3V Power Supply
JN3[1] +5V Power Supply
JN3[2] GND Ground
JN3[3] FP24 Data Output FR0
JN3[4] FP25 “ “ FR1
JN3[5] FP26 “ “ FR2
JN3[6] FP27 “ “ FR3
JN3[7] FP28 “ “ FR4
JN3[8] FP29 “ “ FR5
JN3[9] FP30 “ “ SR0
JN3[10] FP31 “ “ SR1
JN3[11] FP32 “ “ SR2
JN3[12] FP33 “ “ SR3
JN3[13] FP34 “ “ SR4
JN3[14] FP35 “ “ SR5
JN3[15] GND Ground
JN3[16] +5V Power Supply
32 – Reference EPM-CPU-10 Reference Manual