Interfaces and Connectors
EBX-22 Reference Manual
50
R
EFRESHING THE
W
ATCHDOG
If the watchdog timer is enabled, software must periodically refresh the WDHOLD register at a
rate faster than the timer is set to expire. (This is sometimes referred to as “petting” or “feeding”
the watchdog.) To reset the timer, first write 55h to the WDHOLD register (I/O port 1E1h)
followed by AAh to the same register.
W
ATCHDOG
T
IMER
R
EGISTERS
WDSET (Read/Write) 1E0h
D7 D6 D5 D4 D3 D2 D1 D0
ENABLE
EXP6 EXP5 EXP4 EXP3 EXP2 EXP1 EXP0
Table 22: WDSET Register Bit Assignments
Bit Mnemonic
Description
D7 ENABLE
Watchdog Enable
– Enables and disables the watchdog timer reset circuit.
0 = Disabled
1 = Enabled
D6-D0
EXP
Expiration Time –
These bits define the expiration time for the watchdog
timer. The expiration time can be set from 1 to ~16 seconds, or from 08h to
7Fh. See Enabling the Watchdog.
WDHOLD (Read/Write) 1E1h
D7 D6 D5 D4 D3 D2 D1 D0
PET7 PET6 PET5 PET4 PET3 PET2 PET1 PET0
Table 23: WDHOLD Register Bit Assignments
Bit Mnemonic
Description
D7-D0 PET
Pet Watchdog
– If the watchdog timer is enabled, this register must be
periodically refreshed at a rate faster than the timer is set to expire. The code
sequence to hold off a reset is 55h, AAh.
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