Interfaces and Connectors
EBX-22 Reference Manual
44
LVDS
F
LAT
P
ANEL
D
ISPLAY
C
ONNECTOR
The integrated LVDS Flat Panel Display provided through connector J19 on the EBX-22 is an
ANSI/TIA/EIA-644-1995 specification-compliant interface. It can support up to 24 bits of RGB
pixel data plus 3 bits of timing control (HSYNC/VSYNC/DE) on the 4 differential data output
pairs. The LVDS clock frequency ranges from 25 MHz to 112 MHz.
CMOS Setup provides several options for standard LVDS Flat Panel types. If these options do
not match the requirements of the panel you are attempting to use, contact
The 3.3V power provided to pins 19 and 20 of J19 is protected by a 1 Amp fuse.
See the connector location diagram
on page 21 for pin and connector location information.
Table 17: LVDS Flat Panel Display Pinout
J19
Pin
Signal
Name
Function
1 GND
Ground
2 NC
Not
Connected
3
LVDSA3
Diff. Data 3 (+)
4
LVDSA3#
Diff. Data 3 (
-
)
5 GND
Ground
6
LVDSCLK0
Differential Clock (+)
7
LVDSCLK0# Differential Clock (
-
)
8 GND
Ground
9
LVDSA2
Diff. Data 2 (+)
10
LVDSA2#
Diff. Data 2 (
-
)
11 GND
Ground
12
LVDSA1
Diff. Data 1 (+)
13
LVDSA1#
Diff. Data 1 (
-
)
14 GND
Ground
15
LVDSA0
Diff. Data 0 (+)
16
LVDSA0#
Diff. Data 0 (
-
)
17 GND
Ground
18 GND
Ground
19 +3.3V
+3.3V
(Protected)
20 +3.3V
+3.3V
(Protected)
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