Interfaces and Connectors
EPM-32 Reference Manual
35
Video Interface
An on-board video controller integrated into the chipset provides high performance video output
for the EPM-32.
C
ONFIGURATION
The video interface uses PCI interrupt “INTA*”. CMOS Setup is used to select the IRQ line
routed to INTA*.
The EPM-32 uses shared memory architecture. This allows the video controller to use variable
amounts of system DRAM for video RAM. The amount of RAM used for video is set in CMOS
Setup with the Custom Configuration > Video Memory parameter. The default allocation is 8
MB. The maximum allocation is 32 MB.
The EPM-32 supports two types of video output, SVGA and LVDS Flat Panel Display. A CMOS
setup option is used to select which output is enabled after POST.
V
IDEO
BIOS
S
ELECTION
Jumper V1[3-4] can be removed to allow the system to boot off of the Secondary Video BIOS.
Unlike the Primary Video BIOS, the Secondary Video BIOS can be reprogrammed in the field.
SVGA
O
UTPUT
C
ONNECTOR
See the
Connector Location Diagram
on page 15 for the connector location. An adapter cable,
part number VL-CBR-1201, is available to translate JN3 into a standard 15-pin D-Sub SVGA
connector.
This connector uses IEC 61000-4-2-rated TVS components to help protect against ESD damage.
Table 11: JN3 Video Output Pinout
JN3
Pin
Signal
Name
Function
Mini DB15
Pin
1
GND
Ground
6
2
CRED
Red video
1
3
GND
Ground
7
4
CGRN
Green video
2
5
GND
Ground
8
6
CBLU
Blue video
3
7
GND
Ground
5
8
CHSYNC
Horizontal Sync
13
9
GND
Ground
10
10
CVSYNC
Vertical Sync
14
11
NC
Not Connected
–
12
NC
Not Connected
–
