UTAH SCIENTIFIC UTAH-100/UDS 10x10, System Setup And Operation

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1-14 System Setup
Overview
Control Circuitry
The control circuitry for this card is centered around a Freescale K60 MCU and Xilinx
FPGA. The CPU interfaces control inputs from Ethernet and Serial to the FPGA,
which controls all of the switching functions within the router.
FPGA and Memory. The K60 communicates to the XC6SLX9 FPGA (U27) and the
battery backed SRAM (U37). The 16 bit multiplexed Flexbus from the K60 connects to
both of these components to control router switches and store status. FPGA support
circuitry includes the SPI Configuration PROM U36 and programming port J24. There
are two 3 position jumpers –
JP3 – Should always be installed on 1-2.
JP4 - Place on 1-2 to program the FPGA, 2-3 to program the CPU.
Also, sync stripper component U6 receives analog reference and presents H,V, and F
to the FPGA. The front panel switches and LED’s are monitored and controlled by a
soft core processor inside the FPGA.
A general description of the control lines from the FPGA are -
• FPCA1-8. These lines make up two I2C busses, reset and presence
control lines for the front panel.
• SG1-6. Control lines to the Scangate device (Page 8) that allow the CPU
to read the board part number and revision.
• ECON1-8. Two I2C busses and 4 presence lines to the two expansion
connector slots (Page 11)
• A0-7 and XPC0-3. Control lines to the Crosspoint chip (Page 10)
• BISP0-5. SPI control lines to the two bi-directional ports.
• RXn0-1. Control lines that make the bi-directional parts either inputs or
outputs.
• CN0-1. I2C Bus to the two on-board reclocker components.
External port interconnects. The CPU connects to the following external ports -
Ethernet, DB9 and diagnostic RJ-45 serial. The Ethernet port, made up of PHY
component U25 and MagJack J1, is a 10/100 Mb compatible port with no configurable
elements.