BOLT
UDOO BOLT User Manual - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: S.B. - Reviewed by L.V. Copyright © 2019 SECO S.p.A.
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PCIe_REQ0#: PCI Express Clock Request Input, active low signal. This signal shall be driven
low by any module inserted in the connectivity slot, in order to ensure that the SoC makes
available the reference clock.
CONFIG_1: Configuration input signal, +3.3V_RUN signal with 10k
Ω
pull-up. This signal is
necessary to switch between the S-ATA and the PCI-e signals on the pins 41/43/47/49 of
connector CN18. When CONFIG_1 signal is high, then PCI-e x 2 interface is available on
connector CN18. When the signal is driven low, then SATA interface will be available. The
selection is automatic, since according to M.2 specifications for Socket2 SSD modules,
CONFIG_1 signal must be low for SSD based modules and high for PCI-e based modules.
The PCI-e x2 interface can be used also for different purposes other than SSD modules, but it
is important that the CONFIG_1 signal is driven properly (it can be left unconnected on PCI-e
based modules, due to the presence of the pull-up resistor on the platform).
3.3.8
M.2 Connectivity Slot: Socket 1 Key E Type 2230
It is possible to increase the connectivity of the UDOO BOLT
board by using M.2 Socket 1 Key E connectivity modules (i.e.
modules with functionalities like WiFi + Bluetooth).
The connector used for the M.2 Connectivity slot is CN16,
which is a standard 75 pin M.2 Key E connector, type LOTES
p/n APCI0076-P001A, H=4.2mm, with the pinout shown in
the table on the left.
On the UDOO BOLT board there is also a Threaded Spacer which allows the placement of M.2
Socket 1 Key E connectivity modules in 2230 size.
Here following the signals related to this connectivity interface:
/USB_P4-: USB 2.0 Port #4 differential pair.
P/PCIe4_TX-: PCI Express lane #4, Transmitting Output Differential pair
P/PCIe4_RX-: PCI Express lane #4, Receiving Input Differential pair
PCIe / PCIe4_Clock-: PCI Express Reference Clock for lane #4, Differential Pair
M.2_WAKE#: Board
’
s Wake Input, 3.3V_A active low signal. It must be externally driven by the
Connectivity module plugged in the slot when it requires waking up the system.
PLT_RST#: Reset Signal that is sent from the SoC to all PCI-e devices available on the board
59
---
60
---
61
---
62
---
63
---
64
---
65
---
66
---
67
---
68
---
69
CONFIG_1
70
+3.3V_RUN
71
GND
72
+3.3V_RUN
73
GND
74
+3.3V_RUN
75
---
M.2 Connectivity Slot - CN16
Pin Signal
Pin Signal
1
GND
2
+3.3V_ALW
3
4
+3.3V_ALW
5
USB_P4-
6
---
7
GND
8
---
9
---
10
---
11
---
12
---
13
---
14
---
15
---
16
---
17
---
18
GND
19
---
20
---
21
---
22
---
23
---
32
---
33
GND
34
---
35
P
36
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