ZED-F9T - Integration Manual
In safe boot mode the receiver runs from a passive oscillator circuit with less accurate timing and
hence the receiver is unable to communicate via USB.
In this mode only UART1 and DDC communication is possible. For communication via UART1 in safe
boot mode, a training sequence (0x 55 55 at 9600 baud) must be sent by the host to the receiver in
order to begin communication. After this the host must wait at least 2 ms before sending any data.
It is recommended to have the possibility to pull the SAFEBOOT_N pin low in the application. This
can be provided using an externally connected test point or a host I/O port.
3.3.7 TIMEPULSE interface
The ZED-F9T high accuracy timing receiver provides time pulse signals on the TIMEPULSE and
TIMEPULSE 2 pins.
3.3.8 Display data channel (DDC)
An I
2
C compliant DDC interface is available for communication with an external host CPU or u-blox
cellular modules. The interface can be operated in slave mode only. The DDC protocol and electrical
interface are fully compatible with fast-mode of the I
2
C industry standard. Since the maximum SCL
clock frequency is 400 kHz, the maximum transfer rate is 400 kb/s. The SCL and SDA pins have
internal pull-up resistors which should be sufficient for most applications. However, depending on
the speed of the host and the load on the DDC lines additional external pull-up resistors may be
necessary.
To use the DDC/I
2
C interface DSEL pin must be driven low, or left open.
3.3.9 Antenna supervisor
An active antenna supervisor provides the means to check the antenna for open and short circuits
and to shut off the antenna supply if a short circuit is detected. Once enabled, the active antenna
supervisor produces status messages, reporting in NMEA and/or UBX protocol.
The antenna supervisor can be configured through the CFG-HW-ANT_* configuration items. The
current configuration of the active antenna supervisor can also be checked by polling the related
CFG-HW_ANT_* configuration items.
The current active antenna status can be determined by polling the UBX-MON-RF message. If an
antenna is connected, the initial state after power-up is “Active Antenna OK" in the u-center UBX-
MON-RF view.
An active antenna supervisor circuit is connected to the ANT_DET, ANT_OFF, ANT_SHORT_N
pins. For an example the open circuit detection circuit using ANT_DET, "high" = Antenna detected
(antenna consumes current); "low" = Antenna not detected (no current drawn).
The following schematic details the required circuit and the sections following it detail how to enable
and monitor each feature:
UBX-19005590 - R01
3 Receiver functionality
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