ZED-F9T - Integration Manual
3.3.11.5 DDC (I
2
C) port
The display data channel (DDC) bus is a two-wire communication interface compatible with the
I²C
standard.
Unlike all other interfaces, the DDC is not able to communicate in full-duplex mode, i.e. TX and RX
are mutually exclusive. u-blox receivers act as a slave in the communication setup, therefore they
cannot initiate data transfers on their own. The host, which is always master, provides the data clock
(SCL), and the clock frequency is therefore not configurable on the slave.
The receiver's DDC address is set to 0x42 by default.
As the receiver will be run in slave mode and the DDC physical layer lacks a handshake mechanism
to inform the master about data availability, a layer has been inserted between the physical layer
and the UBX and NMEA layer. The receiver DDC interface implements a simple streaming interface
that allows the constant polling of data, discarding everything that is not parse-able. The receiver
returns 0xFF if no data is available. The TX-ready feature can be used to inform the master about
data availability and can be used as a trigger for data transmission.
3.3.11.5.1 Read access
The DDC interface allows 256 slave registers to be addressed. As shown in
Figure 13
only three of
these are currently implemented. The data registers 0 to 252, at addresses 0x00 to 0xFC, each 1
byte in size, contain information to be defined later - the result of reading them is undefined. The
currently available number of bytes in the message stream can be read at addresses 0xFD and
0xFE. The register at address 0xFF allows the data stream to be read. If there is no data awaiting
transmission from the receiver, then this register will deliver the value 0xFF, which cannot be the
first byte of a valid message. If message data is ready for transmission, then successive reads of
register 0xff will deliver the waiting message data.
The registers 0x00 to 0xFC are reserved for future use and may be defined in a later
firmware release. Do not use them, as they don't provide any meaningful data.
Figure 13: DDC register layout
UBX-19005590 - R01
3 Receiver functionality
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