TOBY-L4 series - System Integration Manual
UBX-16024839 - R04
Design-in
Page 88 of 143
2.6.1.2
Guidelines for USB layout design
The
USB_D+
/
USB_D–
,
U
/
USB_SSTX–
and
U
/
USB_SSRX–
lines require accurate layout
design to achieve reliable signaling at the high speed data rates (up to 480 Mbit/s or up to 5 Gbit/s) supported
by the USB 2.0 or USB 3.0 interface.
The characteristic impedance of the
USB_D+
/
USB_D–
,
U
/
USB_SSTX–
and
U
/
USB_SSRX–
lines is specified by the
[3] and the
USB 3.0 specification
[4]. The most important parameter
is the differential characteristic impedance applicable for the odd-mode electromagnetic field, which should be
as close as possible to 90
differential. Signal integrity may be degraded if the PCB layout is not optimal,
especially when the USB signaling lines are very long.
Use the following general routing guidelines to minimize signal quality problems:
Route
USB_D+
/
USB_D–
,
U
/
USB_SSTX–
and
U
/
USB_SSRX–
lines as a differential pair
Route
USB_D+
/
USB_D–
,
U
/
USB_SSTX–
and
U
/
USB_SSRX–
lines as short as possible
Ensure the differential characteristic impedance (Z
0
) is as close as possible to 90
Ensure the common mode characteristic impedance (Z
CM
) is as close as possible to 30
Consider design rules for
USB_D+
/
USB_D–
,
U
/
USB_SSTX–
and
U
/
USB_SSRX–
similar
to RF transmission lines, these being coupled differential micro-strip or buried stripline: avoid any stubs,
abrupt change of layout, and route on clear PCB area
Figure 44 and Figure 45 provide two examples of coplanar waveguide designs with differential characteristic
impedance close to 90
and common mode characteristic impedance close to 30
. The first transmission line
can be implemented for a 4-layer PCB stack-up herein illustrated; the second transmission line can be
implemented for a 2-layer PCB stack-up herein illustrated.
35 µm
35 µm
35 µm
35 µm
270 µm
270 µm
760 µm
L1 Copper
L3 Copper
L2 Copper
L4 Copper
FR-4 dielectric
FR-4 dielectric
FR-4 dielectric
350 µm 400 µm
400 µm
350 µm
400 µm
Figure 44: Example of USB line design, with Z
0
close to 90
and Z
CM
close to 30
, for the described 4-layer board layup
35 µm
35 µm
1510 µm
L2 Copper
L1 Copper
FR-4 dielectric
740 µm 410 µm
410 µm
740 µm
410 µm
Figure 45: Example of USB line design, with Z
0
close to 90
and Z
CM
close to 30
, for the described 2-layer board layup
