LEA-5, NEO-5, TIM-5H - Hardware Integration Manual
GPS.G5-MS5-09027-A2
Released
Hardware description
Page 14 of 68
1.5.3.1
Addresses, roles and modes
Each device connected to a DDC is identified by a unique 7-bit address (e.g. whether it‖s a microcontroller,
EEPROM or D/A Converter, etc) and can operate as either a transmitter or receiver, depending on the function of
the device. The default DDC address for u-blox GPS receivers is set to 0x42. Setting the mode field in the CFG-
PRT message for DDC accordingly can change this address.
The first byte sent is comprised of the address field and R/W bit. Hence the byte seen on the bus 0x42 is
shifted by 1 to the left plus R/W bit thus being 0x84 or 0x85 if analyzed by scope or protocol analyzer.
In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing
data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to
permit that transfer. At that time, any device addressed is considered a slave. The DDC-bus is a multi-master bus,
i.e. multiple devices are capable of controlling the bus. Such architecture is not permanent and depends on the
direction of data transfer at any given point in time. A master device not only allocates the time slots when
slaves can respond but also enables and synchronizes designated slaves to physically access the bus by driving
the clock. Although multiple nodes can assume the role of a master, only one at any time is permitted to do so.
Thus, when one node acts as master, all other nodes act as slaves. Table 2 shows the possible roles and modes
for devices connected to a DDC bus.
Transmit
Receive
Master:
sends the clock and addresses slaves
Sends data to slave
Receives data from slave
Slave:
receives the clock and address
Sends data to master
Receives data from master
Table 2: Possible roles and modes of devices connected to DDC bus
u-blox 5 GPS receivers normally run in the slave mode. There is an exception when an external EEPROM is
attached. In that case, the receiver attempts to establish presence of such a non-volatile memory component by
writing and reading from a specific location. If EEPROM is present (assumed to be located at a fixed address
0xA0), the receiver assumes the role of a master on the bus and never changes role to slave until the following
start-up (subject to EEPROM presence). This process takes place only once at the start-up, i.e. the receiver‖s role
cannot be changed during the normal operation afterward. This model is an exception and should not be
implemented if there are other participants on the bus contending for the bus control (
µ
C / CPU, etc.).
Since the physical layer lacks a handshake mechanism to indicate the data availability, a layer has been inserted
between the physical layer and the UBX and NMEA layer. The DDC implements a simple streaming interface that
allows for constant data polling, discarding the segments of the data stream that do not belong to a valid UBX
or NMEA message. Thus the u-blox GPS receiver returns 0xFf If no data is available. If the polling process is
suspended for an extended period of time of 1.5 sec, the receiver temporarily stops writing data to the output
buffer to prevent overflowing.
As a slave on the bus, the u-blox 5 GPS receiver cannot initiate the data transfers. The master node has the
exclusive right and responsibility to generate the data clock, therefore the slave nodes need not be configured to
use the same baud rate. For the purpose of simplification, if not specified differently, SLAVE denotes the u-blox 5
GPS receiver while MASTER denotes the external device (CPU,
μ
C) controlling the DDC bus by driving the SCL
line.
u-blox GPS receivers support standard mode I
2
C-bus specification with 7-bit addressing and a data
transfer rate up to 100 kbit/s.
1.5.3.2
Communicating to a slave with the GPS receiver as master
Pins SDA2 and SCL2 have internal pull-ups. If capacitive bus load is large, additional external pull-ups may be
needed in order to reduce the pull-up resistance.
Table 3 lists the maximum total pull-up resistor values for the DDC interface. The pull-up resistors integrated in
the pads of the baseband-IC can simply be ignored for high capacitive loads. However, for small loads, e.g. if just
connecting to an external EEPROM, these built-in pull-ups are sufficient.
