u-blox LARA-R203, System Integration Manual

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LARA-R2 series - System Integration Manual
UBX-16010573 - R12 System description
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1.11 Clock output
LARA-R2 series modules provide the master digital clock output function on the
GPIO6
pin, which can be
configured to provide a 13 MHz or 26 MHz square wave. This is mainly designed to feed the master clock input
of an external audio codec, as the clock output can be configured in “Audio dependent” mode (generating the
square wave only when the audio path is active), or in “Continuous” mode.
For more details, see the
u-blox AT Commands Manual [2], +UMCLK AT command.
1.12 General Purpose Input/Output (GPIO)
LARA-R2 series modules include 9 pins (
GPIO1
-
GPIO5
,
I2S_TXD
,
I2S_RXD
,
I2S_CLK
,
I2S_WA
) which can be
configured as General Purpose Input/Output or to provide custom functions via u-blox AT commands (for more
details, see the
u-blox AT Commands Manual [2], +UGPIOC, +UGPIOR, +UGPIOW AT commands), as summarized
in Table 12.
Function Description Default GPIO Configurable GPIOs
Network status
indication Network status: registered home network, registered
roaming, data transmission, no service -- GPIO1-GPIO4
GNSS supply enable
17
Enable/disable the supply of u-blox GNSS receiver
connected to the cellular module GPIO2 GPIO1-GPIO4
GNSS data ready 17 Sense when u-blox GNSS receiver connected to the
module is ready for sending data by the DDC (I
2
C)
GPIO3 GPIO3
GNSS RTC sharing
18
RTC synchronization signal to the u-blox GNSS receiver
connected to the cellular module -- GPIO4
SIM card detection External SIM card physical presence detection GPIO5 GPIO5
SIM card hot
insertion/removal Enable / disable SIM interface upon detection of external
SIM card physical insertion / removal -- GPIO5
I
2
S digital audio
interface
I
2
S digital audio interface I2S_RXD, I2S_TXD,
I2S_CLK, I2S_WA I2S_RXD, I2S_TXD,
I2S_CLK, I2S_WA
Wi-Fi control 18 Control of an external Wi-Fi chip or module -- --
General purpose input Input to sense high or low digital level -- All
General purpose output Output to set the high or the low digital level GPIO4 All
Pin disabled Tri-state with an internal active pull-down enabled GPIO1 All
Table 12: LARA-R2 series GPIO custom functions configuration
1.13 Reserved pins (RSVD)
LARA-R2 series modules have pins reserved for future use, named RSVD : they can all be left unconnected on the
application board, except

the RSVD pin number 33 that must be externally connected to ground
17 Not supported by the LARA-R204-02B and LARA-R211-02B-00 product versions: GPIO2 and GPIO3 pins are by default disabled
18
Not supported by the “02” and “62” product versions