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peripherals that require this area of system memory should have a note
in their user information to that effect.
PCI 2.1 Compliance
Select Enabled to support compliance with PCI specification version
2.1.
Pipeline Cache Timing
If your system contains a single bank of pipelined burst SRAM, select
Faster. If your system contains two banks of pipelined burst SRAM,
select Fastest.
Chipset NA# Asserted
If Disabled, NA# assertion depends upon cache size and type. If
Enabled, the NA# pin is never asserted. Instead, in a process called
“pipelining,” the chipset will signal the CPU for a new memory address
before all the data transfers for the current cycle are complete.
Mem. Drive Str. (MA/RAS)
Stands for Memory Address Drive Strength. Controls the strength of
the output buffers driving the MA and BA1 pins (first value) and
SCASx#, CKEx, MWEx#, and SRASx# pins (second value).
DRAM Refresh Rate
Designates the period required to refresh the DRAMs. Be sure the
value entered is in accordance with your DRAM specifications.
CPU Warning Temperature
LM75 monitors the CPU’s temperature. If the CPU temperature
exceeds the value in this field, a warning beep will sound. Enabled
warning temperature choices are 60, 65, 70, 75, 80, 85, or 90 degrees
Celsius. If Disabled, no beep will sound.
Current CPU Temperature
This display-only field shows the current CPU temperature as detected
by LM75.
BIOS
