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Chipset Features Setup
Auto Configuration
This function selects the optimal values for your chipset parameters. If
Disabled, the chipset parameters will revert to setup information stored
in CMOS. When Auto Configuration is Enabled, many of the options
below will not be available.
DRAM Timing
The value in this field is determined by the performance parameters of
the installed DRAM chips. Unless you install new memory that has a
different performance rating than the factory DRAMs, you should not
alter this field.
DRAM Leadoff Timing
Selects the combination of CPU clocks the DRAM on your board
requires before each read from or write to the memory. Beware:
changing the value from the setting determined by the board designer
for the installed DRAM may cause memory errors.
Chapter 4
ESC : Quit
è ç êé
: Select Item
F1 : Help
PU/PD/+/- : Modify
F5 : Old Values
(Shift)F2 : Color
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
ROM PCI/ISA BIOS (2A59IT5A)
CHIPSET SETUP UTILITY
AWARD SOFTWARE, INC.
Pipeline Cache Timing
: Faster
Chipset NA# Asserted
: Enabled
Mem. Drive Str. (MA/RAS)
: Auto
DRAM Refresh Rate
: 15.6 us
CPU Warning Temperature
: Disabled
Current CPU Temperature
:
35
°
C/ 95
°
F
Auto Configuration
: Enabled
DRAM Timing
: 70ns
DRAM Leadoff Timing
: 10/6/4
DRAM Read Burst (EDO/FP)
: x333/x444
DRAM Write Burst Timing
: x333
Fast EDO Lead Off
: Disabled
Refresh RAS# Assertion
: 5 Clks
Fast RAS To CAS delay
: 3
DRAM Page Idle Timer
: 2 Clks
DRAM Enhanced Paging
: Enabled
Fast MA to RAS# delay
: 2 Clks
SDRAM(CAS Lat/RAS-to-CAS) : 3/3
SDRAM Speculative Read
: Disabled
System BIOS Cacheable
: Disabled
Video BIOS Cacheable
: Disabled
8 Bit I/O Recovery Time
: NA
16 Bit I/O Recover Time
: NA
Memory Hole at 15M-16M
: Disabled
PCI 2.1 Compliance
: Disabled
