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Pentium II Motherboards AMI BIOS Setup -Page
19-
Chipset Setup,
Continued
Fixed Memory Hole This option specifies the location of an area of memory that cannot be addressed on
the ISA bus. The settings are Disabled, 15 MB-16 MB, or 512KB-640KB. The Optimal
and Fail-Safe default settings are Disabled.
CPU To IDE Posting Set this option to Enabled to allow the CPU to post writes from the CPU to the
IDE controller. The settings are Enabled or Disabled. The Optimal and Fail-Safe
default settings are Enabled.
USWC Write Posting Set this option to Enabled to allow write operations from USWC memory to be
posted. The settings are Enabled or Disabled. The Optimal and Fail-Safe default
settings are Disabled.
CPU To PCI Posting Set this option to Enabled to allow write operations from the CPU to be posted to
the PCI bus. The settings are Enabled or Disabled. The Optimal and Fail-Safe default
settings are Enabled.
PCI To DRAM Pipeline Set this option to Enabled to enable the pipeline from the PCI bus to DRAM
system memory. The settings are Enabled or Disabled. The Optimal and Fail-Safe
default settings are Enabled.
PCI Burst Write Combine Set this option to Enabled to enable PCI bus burst write operations to be
combined. The settings are Enabled or Disabled. The Optimal and Fail-Safe default
settings are Enabled.
Read Around Write Set this option to Enabled to enable readaround write operations. The settings are
Enabled or Disabled. The Optimal and Fail-Safe default settings are Enabled.