Page 15
IR104-V4 User Guide
Rev A
Interrupts Control Register (ICR)
The ICR I/O map has one Interrupt Enable (IE) per input and four Interrupt Output enables (IRQen4, IRQen5,
IRQen6 and IRQen7). Each of the Interrupt Outputs correspond to a PC/104 interrupt line. Only one Interrupt
Output should be enabled.
Interrupts are generated and issued on the PC/104 Bus when ALL of the following conditions are met:
1. A change of input state has occurred indicated by the Flag registers.
2. The input that changed has its Interrupt Enable set (logic “1”).
3. One of the Interrupt Output Enables is set (logic “1”).
Bank
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
ICR Bank 1
IE8
IE7
IE6
IE5
IE4
IE3
IE2
IE1
ICR Bank 2
IE16
IE15
IE14
IE13
IE12
IE11
IE10
IE9
ICR Bank 3
IRQen7
IRQen6
IRQen5
IRQen4
IE20
IE19
IE18
IE17
ICR Grouping
Bank
Interrupts
Address
ICR Bank 1
IE1 to IE8
I/O address = Base A 12 (0x0C)
ICR Bank 2
IE9 to IE16
I/O address = Base A 13 (0x0D)
ICR Bank 3
IE17 to IE20 & IRQen4 to 7
I/O address = Base A 14 (0x0E)
ICR I/O Map
Note
An Interrupt will stay asserted until all the Input Change Flags that have their Interrupt Enabled flags enabled are cleared. An
input change flag can be cleared by reading the corresponding input bank.
CAUTION: Equipment Damage
The IR104-V4 interrupts cannot be shared with other PC/104 boards. Attempting to share an IRQ may cause damage to the
IR104-V4 and the other PC/104 board as well.
!
3 Configuration
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