TE0808 TRM
Revision: v.32
Copyright © 2019 Trenz Electronic GmbH
32 of 46
http://www.trenz-electronic.de
8.5 Voltage Monitor Circuit
The voltages LP_DCDC and LP_0V85 are monitored by the voltage monitor circuit U41, which generates the POR_B
reset signal at power-on. A manual reset is also possible by driving the MR-pin (J2-83) to GND. Leave this pin
unconnected or connect to VDD (LP_DCDC) when unused.
Figure 5
: Voltage monitor circuit
8.6 Power Rails
Power Rail
Name
B2B J1 Pins
B2B J2 Pins
B2B J3 Pins
Directions
Note
PL_DCIN
151, 153, 157,
159
-
-
Input
-
DCDCIN
-
154, 156, 158,
160,
153, 155, 157,
159
-
Input
-
LP_DCDC
-
138, 140, 142,
144
-
Input
-
PS_BATT
-
125
-
Input
-
GT_DCDC
-
-
157, 158, 159,
160
Input
-
PLL_3V3
-
-
152
Input
U5
(programma
ble PLL)
3.3V nominal
input
SI_PLL_1V8
-
-
151
Output
Internal
voltage level
1.8V nominal
output
