Trenz Electronic TE0808 TRM, Manual

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TE0808 TRM Revision: v.32
Copyright © 2019 Trenz Electronic GmbH
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8
https://www.xilinx.com/support/documentation/data_sheets/ds925-zynq-ultrascale-plus.pdf
EN_GT_
R J2-95 GT_DC
DC NC7S08
P5X
data
sheet PG_GT_
R J2-91 Externa
l pull-
up
needed
(max.
5.5V),
max.
sink
current
1 mA TPS744
01 data
sheet
EN_GT_
L J2-79 GT_DC
DC NC7S08
P5X
data
sheet PG_GT_
L J2-97 Externa
l pull-
up
needed
(max.
5.5V),
max.
sink
current
1 mA TPS748
01 data
sheet
EN_PLL
_PWR J2-77 6V TPS820
85SIL
data
sheet PG_PLL
_1V8 J2-80 Externa
l pull-
up
needed
(max.
5.5V),
max.
sink
current
1 mA TPS820
85SIL
data
sheet
Table 16 : Recommended operation conditions of DC-DC converter control signals.
Core voltages and main supply voltages have to reach stable state and their "Power Good"-signals have to be
asserted before other voltages like bank's I/O voltages (VCCOx) can be powered up.
It is important that all PS and PL I/Os are tri-stated at power-on until the "Power Good"-signals are high, meaning
that all on-module voltages have become stable and module is properly powered up.
See Xilinx datasheet DS925
8
for additional information. User should also check related base board documentation
when intending base board design for TE0808 SoM.
To avoid any damage to the MPSoC module, check for stabilized on-board voltages in steady state before
powering up the MPSoC's I/O bank voltages VCCOx. All I/Os should be tri-stated during power-on
sequence.
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