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TE0808 TRM

Revision: v.32

Copyright © 2019 Trenz Electronic GmbH

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http://www.trenz-electronic.de

Bank

Type

B2B
Connector

Count of MGT
Lanes

Schematic
Names /
Connector Pins

MGT Bank's
Reference Clock
Inputs

505

GTR

J2

4 GTR lanes

(4 RX / 4 TX)

B505_RX3_N,
B505_RX3_P, pins
J2-52, J2-54
B505_TX3_N,
B505_TX3_P, pins
J2-49, J2-51

B505_RX2_N,
B505_RX2_P, pins
J2-58, J2-60
B505_TX2_N,
B505_TX2_P, pins
J2-55, J2-57

B505_RX1_N,
B505_RX1_P, pins
J2-64, J2-66
B505_TX1_N,
B505_TX1_P, pins
J2-61, J2-63

B505_RX0_N,
B505_RX0_P, pins
J2-70, J2-72
B505_TX0_N,
B505_TX0_P, pins
J2-67, J2-69

2 reference clock
signals
(B505_CLK0,
B505_CLK1) from
B2B connector
J2 (pins J2-10/
J2-12, J2-16/
J2-18) to bank's
pins P25/P26,
M25/M26

2 reference clock
signal
(B505_CLK2,
B505_CLK3) from
programmable
PLL clock
generator U5 to
bank's pins K25/
K26, H25/H26

Table 3

: B2B connector pin-outs of available MGT lanes of the MPSoC.

5.3 JTAG Interface

JTAG access is provided through the MPSoC's PS configuration bank 503 with bank voltage PS_1V8.

JTAG Signal

B2B Connector Pin

TCK

J2-120

TDI

J2-122

TDO

J2-124

TMS

J2-126

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Summary of Contents for TE0808 TRM

Page 1: ...Online version of this document https wiki trenz electronic de display PD TE0808 TRM TE0808 TRM Revision v 32 Exported on 2019 03 18 ...

Page 2: ...Bank Control Signals 18 5 5 Analog Input 18 5 6 Quad SPI Interface 19 6 Boot Process 20 7 On board Peripherals 22 7 1 Flash 22 7 2 DDR4 SDRAM 22 7 3 Programmable PLL Clock Generator 22 7 4 Oscillators 24 7 5 On board LEDs 24 8 Power and Power On Sequence 25 8 1 Power Consumption 25 8 2 Power Distribution Dependencies 26 8 3 Power On Sequence Diagram 28 8 4 Operation Conditions of the DC DC Convert...

Page 3: ...ximum Ratings 39 11 2 Recommended Operating Conditions 40 11 3 Operating Temperature Ranges 41 11 4 Physical Dimensions 41 12 Revision History 43 12 1 Hardware Revision History 43 12 2 Document Change History 43 13 Disclaimer 45 13 1 Data privacy 45 13 2 Document Warranty 45 13 3 Limitation of Liability 45 13 4 Copyright Notice 45 13 5 Technology Licenses 45 13 6 Environmental Protection 45 13 7 R...

Page 4: ...TE0808 TRM Revision v 32 Copyright 2019 Trenz Electronic GmbH 4 of 46 http www trenz electronic de 2 Table of Figures ...

Page 5: ...TE0808 TRM Revision v 32 Copyright 2019 Trenz Electronic GmbH 5 of 46 http www trenz electronic de 3 Table of Tables ...

Page 6: ... trenz org te0808 info for the current online version of this manual and other available documentation 4 1 Key Features MPSoC ZYNQ UltraScale ZU9EG 900 pin package Memory 64 Bit DDR4 8 GByte maximum Dual SPI boot Flash in parallel 512 MByte maximum User I Os 65 x PS MIOs 48 x PL HD GPIOs 156 x PL HP GPIOs 3 banks Serial transceivers 4 x GTR 16 x GTH Transceiver clocks inputs and outputs PLL clock ...

Page 7: ...TE0808 TRM Revision v 32 Copyright 2019 Trenz Electronic GmbH 7 of 46 http www trenz electronic de 4 2 Block Diagram Figure 1 TE0808 04 Block Diagram ...

Page 8: ... U2 7 256Mx16 DDR4 2400 SDRAM U3 8 12A PowerSoC DC DC converter U4 9 Quartz crystal Y1 10 Low power programmable oscillator 25 000000 MHz IN0 for U5 U25 11 10 channel programmable PLL clock generator U5 12 Ultra fine 0 50 mm pitch Razor Beam LP Slim Terminal Strip with 160 contacts J4 13 Ultra fine 0 50 mm pitch Razor Beam LP Slim Terminal Strip with 160 contacts J2 14 Ultra fine 0 50 mm pitch Raz...

Page 9: ...256 Mbit serial NOR Flash memory U7 18 256 Mbit serial NOR Flash memory U17 4 4 Initial Delivery State Storage device name Content Notes SPI Flash main array Not programmed eFUSE Security Not programmed Si5345A programmable PLL NVM OTP Not programmed Table 1 Initial Delivery State of the flash memories ...

Page 10: ...ar units of the Zynq UltraScale MPSoC like I O banks interfaces and Gigabit transceivers or to the on board peripherals Following table lists the I O bank signals which are routed from the MPSoC s PL and PS banks as LVDS pairs or single ended I O s to the B2B connectors Bank Type B2B Connecto r Schemati c Names Connecto r Pins I O Signals LVDS Pairs VCCO Bank Voltage Notes 47 HD J3 B47_L1_P B47_L1...

Page 11: ... N B_64_T0 B_64_T3 52 I O s 24 VCCO64 pins J4 58 J4 106 VCCO max 1 8V usable as single ended I Os 65 HP J4 B65_L1_P B65_L24_ P B65_L1_N B65_L24_ N B_65_T0 B_65_T3 52 I Os 24 VCCO65 pins J4 69 J4 105 VCCO max 1 8V usable as single ended I Os 66 HP J1 B66_L1_P B66_L24_ P B66_L1_N B66_L24_ N B_66_T0 B_66_T3 48 I Os 24 VCCO66 pins J1 90 J1 120 VCCO max 1 8V usable as single ended I Os 500 MIO J3 MIO13...

Page 12: ...om on module DC DC power rail All PL I O Banks have separate VCCO pins in the B2B connectors valid VCCO should be supplied from the baseboard For detailed information about the B2B pin out please refer to the Pin out1 table The configuration of the I O s MIO13 MIO77 are depending on the base board peripherals connected to these pins 5 2 MGT Lanes The B2B connector J1 and J2 provide also access to ...

Page 13: ...51 J1 53 B228_TX3_P B228_TX3_N pins J1 50 J1 52 B228_RX2_P B228_RX2_N pins J1 57 J1 59 B228_TX2_P B228_TX2_N pins J1 56 J1 58 B228_RX1_P B228_RX1_N pins J1 63 J1 65 B228_TX1_P B228_TX1_N pins J1 62 J1 63 B228_RX0_P B228_RX0_N pins J1 69 J1 71 B228_TX0_P B228_TX0_N pins J1 68 J1 70 1 reference clock signal B228_CLK0 from B2B connector J3 pins J3 60 J3 62 to bank s pins R8 R7 1 reference clock signa...

Page 14: ...27 J1 29 B229_TX3_P B229_TX3_N pins J1 26 J1 28 B229_RX2_P B229_RX2_N pins J1 33 J1 35 B229_TX2_P B229_TX2_N pins J1 32 J1 34 B229_RX1_P B229_RX1_N pins J1 39 J1 41 B229_TX1_P B229_TX1_N pins J1 38 J1 40 B229_RX0_P B229_RX0_N pins J1 45 J1 47 B229_TX0_P B229_TX0_N pins J1 44 J1 46 1 reference clock signal B229_CLK0 from B2B connector J3 pins J3 65 J3 67 to bank s pins L8 L7 1 reference clock signa...

Page 15: ...J1 3 J1 5 B230_TX3_P B230_TX3_N pins J1 2 J1 4 B230_RX2_P B230_RX2_N pins J1 9 J1 11 B230_TX2_P B230_TX2_N pins J1 8 J1 10 B230_RX1_P B230_RX1_N pins J1 15 J1 17 B230_TX1_P B230_TX1_N pins J1 14 J1 16 B230_RX0_P B230_RX0_N pins J1 21 J1 23 B230_TX0_P B230_TX0_N pins J1 20 J1 22 1 reference clock signal B230_CLK1 from B2B connector J3 pins J3 59 J3 61 to bank s pins G8 G7 1 reference clock signal B...

Page 16: ... J2 30 B128_TX3_N B128_TX3_P pins J2 25 J2 27 B128_RX2_N B128_RX2_P pins J2 34 J2 36 B128_TX2_N B128_TX2_P pins J2 31 J2 33 B128_RX1_N B128_RX1_P pins J2 40 J2 42 B128_TX1_N B128_TX1_P pins J2 37 J2 39 B128_RX0_N B128_RX0_P pins J2 46 J2 48 B128_TX0_N B128_TX0_P pins J2 43 J2 45 1 reference clock signal B128_CLK1 from B2B connector J2 pins J2 22 J2 24 to bank s pins D25 D26 1 reference clock signa...

Page 17: ...2 64 J2 66 B505_TX1_N B505_TX1_P pins J2 61 J2 63 B505_RX0_N B505_RX0_P pins J2 70 J2 72 B505_TX0_N B505_TX0_P pins J2 67 J2 69 2 reference clock signals B505_CLK0 B505_CLK1 from B2B connector J2 pins J2 10 J2 12 J2 16 J2 18 to bank s pins P25 P26 M25 M26 2 reference clock signal B505_CLK2 B505_CLK3 from programmable PLL clock generator U5 to bank s pins K25 K26 H25 H26 Table 3 B2B connector pin o...

Page 18: ...tion User Guide3 Signal B2B Connector Pin Function DONE J2 116 PL configuration completed PROG_B J2 100 PL configuration reset signal INIT_B J2 98 PS is initialized after a power on reset SRST_B J2 96 System reset MODE0 MODE3 J2 109 J2 107 J2 105 J2 103 4 bit boot mode pins For further information about the boot modes refer to the Xilinx Zynq UltraScale MPSoC TRM section Boot and Configuration ERR...

Page 19: ...I Interface Quad SPI Flash memory ICs U7 and U17 are connected to the Zynq MPSoC PS QSPI0 interface via PS MIO bank 500 pins MIO0 MIO5 and MIO7 MIO12 MI O Signal Name U7 Pin MI O Signal Name U17 Pin 0 SPI Flash CLK B2 7 SPI Flash CS C2 1 SPI Flash IO1 D2 8 SPI Flash IO0 D3 2 SPI Flash IO2 C4 9 SPI Flash IO1 D2 3 SPI Flash IO3 D4 10 SPI Flash IO2 C4 4 SPI Flash IO0 D3 11 SPI Flash IO3 D4 5 SPI Flas...

Page 20: ...de by the pins PS_MODE0 PS_MODE3 little endian alignment Boot Mode Mode Pins 3 0 MIO Location Description JTAG 0x0 JTAG Dedicated PS interface QSPI32 0x2 MIO 12 0 Configured on module with dual QSPI Flash Memory 32 bit addressing Supports single and dual parallel configurations Stack and dual stack is not supported SD0 0x3 MIO 25 13 Supports SD 2 0 SD1 0x5 MIO 51 38 Supports SD 2 0 eMMC_18 0x6 MIO...

Page 21: ...ight 2019 Trenz Electronic GmbH 21 of 46 http www trenz electronic de 4 https www xilinx com support documentation user_guides ug1085 zynq ultrascale trm pdf For functional details see ug1085 Zynq UltraScale TRM Boot Modes Section 4 ...

Page 22: ...DR4 SDRAM The TE0808 04 SoM is equipped with with four DDR4 2400 SDRAM modules with up to 8 GByte memory density The SDRAM modules are connected to the Zynq MPSoC s PS DDR controller bank 504 with a 64 bit data bus Refer to the Xilinx Zynq UltraScale datasheet DS9255 for more information on whether the specific package of the Zynq UltraScale MPSoC supports the maximum data transmission rate of 240...

Page 23: ...2B Connector pins J2 13 J2 15 differential pair User Default off OUT8 B2B Connector pins J2 7 J2 9 differential pair User Default off OUT9 IN3 Loop back User Default off XA XB Quartz Y1 50 000 MHz Table 11 Programmable PLL clock generator input output The Si5345A programmable clock generator s control interface pins are exposed to B2B connector J2 For further information refer to the Si5345A data ...

Page 24: ...4 Oscillators The TE0808 04 SoM is equipped with two on board oscillators to provide the Zynq s MPSoC s PS configuration bank 503 with reference clock signals Clock Frequency Bank 503 Pin Connected to PS_CLK 33 333333 MHz P20 MEMS Oscillator U32 PS_PAD RTC 32 768 kHz R22 R23 Quartz crystal Y2 Table 13 Reference clock signals to PS configuration bank 503 7 5 On board LEDs LED Color Connected to Des...

Page 25: ...us multi processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features This features allow to offset the power and heat constraints against overall performance and operational efficiency This features allowing highly flexible power management are achieved by establi...

Page 26: ... DCDCIN LP_DCDC PL_DCIN PS_BATT have to be powered up on the assigned pins of the B2B connectors as listed on the section Power Rails Except PS_BATT see section Recommended Operation Conditions all power rails can be powered from 3 3V power sources also share the same source if power domain control is not required There are following dependencies how the initial voltages of the power rails on the ...

Page 27: ...yright 2019 Trenz Electronic GmbH 27 of 46 http www trenz electronic de Figure 3 Power Distribution Diagram Current rating of Samtec Razor Beam LP Terminal Socket Strip ST5 SS5 B2B connectors is 1 5 A per pin 1 pin powered per row ...

Page 28: ...ctivating the above mentioned power rails and the Enable Signals of the DC DC converters The on board voltages will be powered up at three steps 1 Low Power Domain LPD and on board Si5345A programmable clock generator supply voltage 2 Programmable Logic PL and Full Power Domain FPD 3 GTH PS GTR transceiver and DDR memory Hence those three power instances will be powered up consecutively and the Po...

Page 29: ...nz electronic de Figure 4 Power On Sequence Utilizing DC DC Converter Control Signals 8 4 Operation Conditions of the DC DC Converter Control Signals The control signals have to be asserted on the B2B connector J2 whereby some of the Power Good signals need external pull up resistors ...

Page 30: ... EN_FPD J2 102 DCDCIN NC7S08 P5X data sheet PG_FPD J2 110 4K7 pulled up to DCDCIN EN_PL J2 101 PL_DCI N left floating for logic high drive to GND for logic low PG_PL J2 104 Externa l pull up needed max voltage GT_DC DC max sink current 1 mA TPS820 85SIL NC7S08 P5X data sheet EN_DD R J2 112 DCDCIN NC7S08 P5X data sheet PG_DD R J2 114 4K7 pulled up to DCDCIN EN_PSG T J2 84 DCDCIN NC7S08 P5X data she...

Page 31: ...16 Recommended operation conditions of DC DC converter control signals Core voltages and main supply voltages have to reach stable state and their Power Good signals have to be asserted before other voltages like bank s I O voltages VCCOx can be powered up It is important that all PS and PL I Os are tri stated at power on until the Power Good signals are high meaning that all on module voltages ha...

Page 32: ... by driving the MR pin J2 83 to GND Leave this pin unconnected or connect to VDD LP_DCDC when unused Figure 5 Voltage monitor circuit 8 6 Power Rails Power Rail Name B2B J1 Pins B2B J2 Pins B2B J3 Pins Directions Note PL_DCIN 151 153 157 159 Input DCDCIN 154 156 158 160 153 155 157 159 Input LP_DCDC 138 140 142 144 Input PS_BATT 125 Input GT_DCDC 157 158 159 160 Input PLL_3V3 152 Input U5 programm...

Page 33: ...l 1 2V nominal output Table 17 Power rails of the MPSoC module on accessible connectors 8 7 Bank Voltages Bank Type Schematic Name B2B Connector Pins Voltage Reference Input Voltage Voltage Range 47 HD VCCO47 pins J3 43 J3 44 user max 3 3V 48 HD VCCO48 pins J3 15 J3 16 user max 3 3V 64 HP VCCO64 J4 58 J4 106 user VREF_64 pin J4 88 max 1 8V 65 HP VCCO65 J4 69 J4 105 user VREF_65 pin J4 15 max 1 8V ...

Page 34: ...TE0808 TRM Revision v 32 Copyright 2019 Trenz Electronic GmbH 34 of 46 http www trenz electronic de Table 18 Range of MPSoC module s bank voltages ...

Page 35: ...s per row Ultrafine 0197 0 50 mm pitch Narrow body design saves space on board Lead style 03 5 Samtec 28 Gbps Solution Mates with ST5 Insulator Material Liquid Crystal Polymer schwarz Operating Temperature Range 55 C bis 125 C Lead Free Solderable Yes RoHS Konform Yes 9 2 Connector Stacking height When using the standard type on baseboard and module the mating height is 5 mm Other mating heights a...

Page 36: ...quest 9 3 Current Rating Current rating of Samtec Razor Beam LP Terminal Socket Strip ST5 SS5 B2B connectors is 1 5 A per pin 1 pin powered per row 9 4 Connector Speed Ratings The connector speed rating depends on the stacking height Stacking height Speed rating 4 mm Single Ended 13GHz 26Gbps 4 mm Differential 13 5GHz 27Gbps 5 mm Single Ended 13 5GHz 27Gbps 5 mm Differential 20GHz 40 Gbps The SS5 ...

Page 37: ...ic de display j hartfiel 16 https wiki trenz electronic de display j hartfiel 17 https wiki trenz electronic de display j hartfiel 18 https wiki trenz electronic de display j hartfiel 19 https wiki trenz electronic de display j hartfiel Geändert 30 05 2017 by Susanne Kunath12 13 11 2017 by John Hartfiel13 13 11 2017 by John Hartfiel14 13 11 2017 by John Hartfiel15 13 11 2017 by John Hartfiel16 13 ...

Page 38: ... XCZU9EG 1FFV C900E 2GB 0 C 100 C Extended Temperature Range TE0808 04 09 EG 1EB XCZU9EG 1FFV C900E 4GB 0 C 100 C Extended Temperature Range TE0808 04 09 EG 1ED 1 XCZU9EG 1FFV C900E 4GB 0 C 100 C Extended Temperature Range TE0808 04 09 EG 2IB XCZU9EG 2FFV C900I 4GB 40 C 100 C Industrial Temperature Range 1 Note Lower B2B connector profile check distance bolt of between module and carrier Table 19 ...

Page 39: ...3 8 V Si5345 44 42 data sheet VCCO for HD I O banks 0 5 3 4 V Xilinx DS925 data sheet VCCO for HP I O banks 0 5 2 V Xilinx DS925 data sheet VREF 0 5 2 V Xilinx DS925 data sheet I O input voltage for HD I O banks 0 55 VCCO 0 55 V Xilinx DS925 data sheet I O input voltage for HP I O banks 0 55 VCCO 0 55 V Xilinx DS925 data sheet PS I O input voltage MIO pins 0 5 VCCO_PSIO 0 55 V Xilinx DS925 data sh...

Page 40: ...sheet 11 2 Recommended Operating Conditions Parameter Min Max Unit Notes Reference Document PL_DCIN 2 5 6 V EN63A0QI TPS82085SIL data sheet Note PG_PL will be pullup with this voltage DCDCIN 3 1 6 V TPS82085SIL TPS51206PSQ data sheet LP_DCDC 2 5 3 6 V TPS82085SIL TPS3106 data sheet GT_DCDC 2 5 6 V TPS82085SIL data sheet PS_BATT 1 2 1 5 V Xilinx DS925 data sheet PLL_3V3 3 14 3 47 V Si5345 44 42 dat...

Page 41: ...et see schematic for VCC Voltage on input pin MR of TPS3106K33DBVR Voltage Monitor U41 0 VDD V TPS3106 data sheet VDD LP_DCDC 11 3 Operating Temperature Ranges Commercial grade 0 C to 70 C Industrial grade 40 C to 85 C Extended grade 0 C to 85 C The module operating temperature range depends also on customer design and cooling solution Please contact us for options 11 4 Physical Dimensions Module ...

Page 42: ...TE0808 TRM Revision v 32 Copyright 2019 Trenz Electronic GmbH 42 of 46 http www trenz electronic de ...

Page 43: ...ware Revision History Date Revision Notes Link to PCN Documentati on Link 04 First production silicon TE0808 0421 03 Second ES production release TE0808 0322 2016 03 09 02 First ES production release TE0808 0223 01 Prototypes Hardware revision number is written on the PCB board together with the module model number separated by the dash 12 2 Document Change History Date Revision Contributors Descr...

Page 44: ... pin 2017 11 13 v 22 John Hartfiel rework B2B section 2017 10 20 v 21 Ali Naseri Update links pdf documentation to revision 4 ES silicon note removed 2017 08 28 v 15 John Hartfiel Update section Variants Currently In Production 2017 08 28 v 14 Jan Kumann Block diagram changed SPI flash section fixed Few smaller improvements 2017 08 15 v 12 Vitali Tsiukala Changed signals count in the B2B connector...

Page 45: ...any damages whatsoever including without limitation those resulting from lost profits lost data or business interruption arising out of the use inability to use or the results of use of this document any documents linked to this document or the materials or information contained at any or all such documents If your use of the materials or information from this document results in the need for serv...

Page 46: ... European Union in accordance with Directive 2002 96 EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment WEEE Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment...

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