TE0726 TRM
Revision: V.3
Copyright © 2017 Trenz Electronic GmbH
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9
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http://www.trenz-electronic.de
FPGA IO Banks Pin Mapping
Bank
Zynq Pin
Name
Connected To
34
G14
PUDC
Jumper J14
35
G15
DSI_XA
System Controller CPLD, pin 16
35
F15
DSI_XB
System Controller CPLD, pin 17
GPIO to Header J8 Interface Mapping
GPIO
Zynq Pin
J8 Pin
GPIO
Zynq Pin
J8 Pin
GPIO2
K15
3
GPIO15
N13
10
GPIO3
J14
5
GPIO16
L13
36
GPIO4
H12
7
GPIO17
G11
11
GPIO5
N14
29
GPIO18
H11
12
GPIO6
R15
31
GPIO19
R12
35
GPIO7
L14
26
GPIO20
M14
38
GPIO8
L15
24
GPIO21
P15
40
GPIO9
J13
21
GPIO22
H13
15
GPIO19
H14
19
GPIO23
J11
16
GPIO11
J15
23
GPIO24
K11
18
GPIO12
M15
32
GPIO25
K13
22
GPIO13
R13
33
GPIO26
L12
37
GPIO14
M12
8
GPIO27
G12
13