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Spartan-3E FPGA Industrial Micromodule

User Manual

Two   suitable   ways   of   shirt-circuiting   the 
paid   pair   are   by   means   of   a   zero-ohm 
0603   (1608   metric)   chip   resistor   or   a 
solder blob.

FPGA User I/Os

A total of 110 FPGA user I/Os are available 
on corresponding contacts of B2B connect-
ors J4 and J5 (see Appendix).

37 differential digital I/O pairs:
each pair is configurable as 2 single-en-
ded   digital   I/Os,   corresponding   to   a 
maximum   of   74   single-ended   digital 
I/Os;

4 differential clock input pairs:
each pair  is  configurable  as differential 
digital  I/O pair or 2 single-ended clock 
inputs or 2 single-ended digital I/Os (or 
combination   thereof),   corresponding   to 
from a maximum of 8 independent clock 
inputs to a maximum of 8 independent 
digital I/Os;

1 differential clock input pair:
the   pair   is   configurable   as   differential 
digital   input   pair   or   as   2   single-ended 
clock inputs or 2 single-ended digital in-
puts   (or   combination   thereof),   corres-
ponding to from a maximum of 2 inde-
pendent clock inputs to a maximum of 2 
independent digital inputs;

21 single-ended digital I/Os;

5 single-ended inputs.

Table   4  summarizes   the   maximum   avail-
able   FPGA   user   I/Os   divided   by   supply 
voltage.

type

VccIO

3.3 V

diff. I/O pairs

≤ 18

≤ 23

diff inputs

≤ 1

none

diff. clocks

≤ 4

≤ 1

s. e. I/Os

≤ 46

≤ 58

s. e. inputs

≤ 2

≤ 4

s. e. clocks

≤ 8

≤ 3

Table 4: maximum FPGA user I/Os by 
supply voltage.

Differential Pairs

The micromodule has a total of 42 differ-
ential   signal   pairs   routed   pairwise   with   a 
differential impedance of 100 ohm to adja-
cent   connector   pins.   These   lines   can   be 
used   for   high   speed   signaling   up   to 
666 Mbit/s  per differential  pair (see Xilinx 
Application Note XAPP485).

User Button and LED

LED

The   LED   is   lit   when   the   U_LED   line   (pin 
R10) is set high as detailed in the follow-
ing table.

Signal

FPGA pin

FPGA ball

U_LED

IO_L15P_2

(bank 2)

R10

Table 5: user led signal details.

Push Button

The push button is connected to the PB in-
put (pin V16). as detailed in the following 
table.

Trenz Electronic GmbH

6

Figure 10: R103 pad pair (blue high-
light) for 2.5 V internal supply.

Figure 9: R102 pad pair (blue high-
light) for 3.3 V internal supply.

Summary of Contents for TE0300

Page 1: ...ss mainly focus on the distribution of electronic components Line cards we deal with include Microchip ALPS ROHM Xilinx Pulse ON Everlight and Freescale Main products comprise IC Modules Potentiometer...

Page 2: ...to board connectors Most I O s on the B2B connectors are routed as LVDS pairs Evenly spread supply pins for good signal integrity Industrial temperature grade avail able on request Low cost versatile...

Page 3: ...Power Supply 5 FPGA User I Os 6 User Button and LED 7 Configuration Switches 7 JTAG and SPI 8 Clock Networks 9 On board Memories 10 Module Configuration 11 Changes from TE0300 00 to TE0300 01 24 Order...

Page 4: ...carrier boards It is a powerful system widely used for educational and research activities Boards with other configurations larger FPGA s or equipped with industrial temper ature grade parts are avail...

Page 5: ...0300 receptacle with its corresponding header The stacking height of the TE0300 B2B connectors is 7 seven mm The stacking height does not include the solder paste thickness USB Connector The micromodu...

Page 6: ...t used on the baseboard it is re commended to bypass them to ground with 10 nF 100 nF capacitors I O Banks Power Supply The Spartan 3E architecture organizes I Os into four I O banks see Table 3 Bank...

Page 7: ...from a maximum of 2 inde pendent clock inputs to a maximum of 2 independent digital inputs 21 single ended digital I Os 5 single ended inputs Table 4 summarizes the maximum avail able FPGA user I Os...

Page 8: ...emory in direct mode For programming the SPI Flash memory in indirect mode over JTAG S2 has to be turned on Run S2 position Run on system running Reset off system reset Table 8 S2 default Run For furt...

Page 9: ...I Serial Flash and XAPP974 Indirect Pro gramming of SPI Serial Flash PROMs with Spartan 3A FPGAs S4 position SPI on FPGA configuration JTAG SPI JTAG off FPGA configuration JTAG Table 10 S4 default SPI...

Page 10: ...I programmer with flying leads as described in Table 13 Signal FPGA pin FPGA ball SPI S IO_L01P_2 U3 SPI D IO_L03N_2 T4 SPI Q IO_L16N_2 N10 SPI C IO_L26N_2 U16 Table 12 SPI signal details bank 2 SPI S...

Page 11: ...3 Digital Clock Manager DCM The DCMs of the FPGA can be used to syn thesize arbitrary clock frequencies from any on board clock network differential clock input pair or single ended clock in put For f...

Page 12: ...e configuration of the TE0300 module However only through the JTAG interface it is possible to develop and de bug with Xilinx tools e g Xilinx Chip Scope Xilinx Microprocessor Debugger The SPI interfa...

Page 13: ...ed on the host computer then the easiest way to do it is the following disconnect the micromodule or leave the micromodule unconnected configure the micromodule such that the USB microcontroller will...

Page 14: ...t S1 is actually switched to EEPROM The USB EEPROM can be programmed by opening the dedicated software Cypress USB Console double click the CyCon sole exe file in the 1st_program CyCon sole folder Cli...

Page 15: ...wing table DIP switch on left off right S1 EEPROM S2 Run S3 FX2 PON S4 X X Reconnect the USB cable to run the newly uploaded firmware in the USB microcon troller Under the default switch configura tio...

Page 16: ...300 micromodule can be con figured by means of a firmware upgrade FWU file see next section Micromodule Configuration for further reference The first step in generating the FWU file is to generate the...

Page 17: ...l Select prepare PROM file Select BIN as output Set PROM File Name to fpga and change Location to a suitable name and location Check Auto Select PROM Navigate to your project s IMPLEMENTA TION folder...

Page 18: ...ule User Manual The following warning is a normal situ ation This is probably the one and only file with your design Congratulations Click GENERATE FILE or select from menu Operations Generate file Yo...

Page 19: ...nchanged zip the 3 files change the zip file extension to fwu upload the file as explained in the next section Micromodule Configuration Warning file and path names are given and must NOT be changed M...

Page 20: ...folder To generate your own firmware upload file please read the document Generating_FWU_file doc in the USB FWUTool folder SPI Direct In System Programming ISP Make sure S2 is switched to Reset off...

Page 21: ...ce blinking mcs in the TE0300 folder Select the part name corresponding to the SPI flash present on the module STMicro electronics M25P32 a 32 Mbit 4M x 8 Serial Flash memory iMPACT should now look li...

Page 22: ...t 0 5 Hz For further information about direct pure SPI in system programming of SPI Flash memories please see Xilinx Application Note XAPP951 Configuring Xilinx FPGAs with SPI Serial Flash SPI Indirec...

Page 23: ...king bit in the TE0300 folder Do not forget to select the Enable Programming of SPI Flash Device Attached to this FPGA option in the same window An Add PROM File dialog window should pop up automatica...

Page 24: ...Program operation In the Device Programming Properties window just leave the default settings and press the OK button iMPACT will first erase the memory and then write it After successful programming...

Page 25: ...een ex tended from an input in TE0300 00 to an I O in TE0300 01 Therefore hardware designs developed for the TE0300 00 are compatible with the TE0300 01 whereas those developed for the TE0300 01 are c...

Page 26: ...does not warrant the accuracy and completeness of the materials in this document Further to the maximum ex tent permitted by applicable law Trenz Electronic disclaims all warranties either express or...

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