•
PCI Master 0 WS Write
When “Enabled”, writes to the PCI bus are executed with zero wait states.
•
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions
cycles. Select “Enabled” to support compliance with PCI specification version 2.1.
•
PCI Master Read Caching
Options are: “Enabled” and “Disabled”.
•
PCI #2 Access #1 Retry
Options are: “Enabled” and “Disabled”.
•
AGP Master 1 WS Write
Selecting “Enabled” will implement a single delay when writing to the AGP Bus. By
default, two wait states are used by the system, allowing for greater stability.
•
AGP Master 1 WS Read
This implements a single delay when reading to the AGP Bus. By default, two-wait
states are used by the system, allowing for greater stability.
•
Memory Parity/ECC Check
When parity DRAM modules are installed, select “Enabled” to correct 1 bit memory
errors in the memory. Otherwise, select “Disabled”.
BIOS SETUP
32
Transcend Information, Inc.
