TQ-Systems TQMa6x, User Manual

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User's Manual l TQMa6x & TQMa6xP UM 0403 l © 2019, TQ-Systems GmbH Page 37
3.3.2 Pinout connector X1 (continued)
Table 50: Pinout connector X1 (continued)
Ball I/O Level Group Signal Pin Signal Group Level I/O Ball
L1 I 3.3 V UART UART4_RX 81 82 GPIO5_IO18 GPIO 3.3 V I/O P1
M2 O 3.3 V UART UART4_TX 83 84 GPIO5_IO21 GPIO 3.3 V I/O N2
L4 I 3.3 V UART UART4_RTS# 85 86 I2C3_SCL I2C 3.3 V O
PU
R4
L3 O 3.3 V UART UART4_CTS# 87 88 I2C3_SDA I2C 3.3 V I/O
PU
T3
M5 I 3.3 V UART UART5_RX 89 90 CAN2_RX CAN 3.3 V I V5
M4 O 3.3 V UART UART5_TX 91 92 CAN2_TX CAN 3.3 V O T6
M6 I 3.3 V UART UART5_RTS# 93 94 CAN1_RX CAN 3.3 V I W4
L6 O 3.3 V UART UART5_CTS# 95 96 CAN1_TX CAN 3.3 V O W6
– P 0 V POWER DGND 97 98 DGND POWER 0 V P –
M1 I 3.3 V AUDIO AUD3_RXC 99 100 AUD3_TXC AUDIO 3.3 V O N1
M3 I 3.3 V AUDIO AUD3_RXFS 101 102 AUD3_TXFS AUDIO 3.3 V O N4
N3 I 3.3 V AUDIO AUD3_RXD 103 104 AUD3_TXD AUDIO 3.3 V O P2
F17 O 3.3 V PWM PWM4 105 106 GPIO1_IO21 GPIO 3.3 V I/O F18
N5 O 3.3 V I2C I2C1_SCL 107 108 SPI5_MISO SPI 3.3 V I A21
N6 I/O 3.3 V I2C I2C1_SDA 109 110 SPI5_MOSI SPI 3.3 V O B21
P3 I/O 3.3 V GPIO GPIO5_IO20 111 112 SPI5_SS0# SPI 3.3 V O C20
P5 I/O 3.3 V GPIO GPIO4_IO05 113 114 SPI5_SCK SPI 3.3 V O D20
– P 0 V POWER DGND 115 116 DGND POWER 0 V P –
Y1 O
–
21
LVDS LVDS1_TX0_N 117 118 LVDS0_TX0_N LVDS
–
21
O U2
Y2 O –
21
LVDS LVDS1_TX0_P 119 120 LVDS0_TX0_P LVDS –
21
O U1
– P 0 V POWER DGND 121 122 DGND POWER 0 V P –
AA2 O –
21
LVDS LVDS1_TX1_N 123 124 LVDS0_TX1_N LVDS –
21
O U4
AA1 O –
21
LVDS LVDS1_TX1_P 125 126 LVDS0_TX1_P LVDS –
21
O U3
– P 0 V POWER DGND 127 128 DGND POWER 0 V P –
AB1 O
–
21
LVDS LVDS1_TX2_N 129 130 LVDS0_TX2_N LVDS
–
21
O V2
AB2 O
–
21
LVDS LVDS1_TX2_P 131 132 LVDS0_TX2_P LVDS
–
21
O V1
– P 0 V POWER DGND 133 134 DGND POWER 0 V P –
Y3 O
–
21
LVDS LVDS1_CLK_N 135 136 LVDS0_CLK_N LVDS
–
21
O V4
Y4 O
–
21
LVDS LVDS1_CLK_P 137 138 LVDS0_CLK_P LVDS
–
21
O V3
– P 0 V POWER DGND 139 140 DGND POWER 0 V P –
AA3 O
–
21
LVDS LVDS1_TX3_N 141 142 LVDS0_TX3_N LVDS
–
21
O W2
AA4 O
–
21
LVDS LVDS1_TX3_P 143 144 LVDS0_TX3_P LVDS
–
21
O W1
– P 0 V POWER DGND 145 146 DGND POWER 0 V P –
T2 O 3.3 V PWM PWM1 147 148 GPIO7_IO13 GPIO 3.3 V I/O P6
U20 I/O ENET
22
GPIO GPIO1_IO30 149 150 GPIO7_IO11 GPIO 3.3 V I/O R2
W20 I/O ENET
22
GPIO GPIO1_IO29 151 152 GPIO1_IO07 GPIO 3.3 V I/O R3
V21 I/O ENET
22
GPIO GPIO1_IO28 153 154 GPIO1_IO26 GPIO ENET
22
I/O W22
U21 I/O
ENET
22
GPIO GPIO1_IO25 155 156 SPDIF_OUT AUDIO
ENET
22
O W21
R5 I/O 3.3 V GPIO GPIO1_IO08 157 158 SPDIF_IN AUDIO
ENET
22
I W23
– P 0 V POWER DGND 159 160 DGND POWER 0 V P –
21: See LVDS Specification (ANSI EIA-644-A).
22: 2.5 V if NVCC_ENET_IN is connected to VCC2V5_RGMII_OUT. 3.3 V if NVCC_ENET_IN is connected to VCC3V3_REF_OUT.