User's Manual l TQMa6x & TQMa6xP UM 0403 l © 2019, TQ-Systems GmbH
Page 12
3.2.2
Memory
3.2.2.1
DDR3L SDRAM
Depending on the i.MX6 derivative either two or four DDR3L SDRAM chips are assembled on the TQMa6x.
All chips have one common chip select. The chips are connected to the i.MX6 with a 64-bit bus.
(Exception: The i.MX6 “Solo” is connected with a 32-bit bus.)
The following block diagram shows how the DDR3L SDRAM is connected to the i.MX6.
i.MX6
DDR3L#1 Top
DDR3L#2 Top
DDR3L#1 Bot
A[15:0]
D[15:0]
D[31:16]
CS0#
CTRL
DDR3L#2 Bot
CLK1
D[47:32]
D[63:48]
CLK0
DQM[M;S][3:0]
DQM[M;S][7:4]
Illustration 3:
Block diagram DDR3L SDRAM connection
The characteristics of the memory interface depend on the i.MX6 derivative.
The following table shows the different possibilities.
Table 10:
i.MX6 SDRAM interface according to i.MX6 derivative
i.MX6 derivative
Bus width
Clock
SDRAM chips
i.MX6 Solo
× 32
396 MHz
2
Yes
i.MX6 DualLite
× 64
396 MHz
4
Yes
i.MX6 Dual
× 64
528 MHz
4
Yes
i.MX6 DualPlus
× 64
528 MHz
4
Yes
i.MX6 Quad
× 64
528 MHz
4
Yes
i.MX6 QuadPlus
× 64
528 MHz
4
Yes
The assembly options of DDR3L SDRAM on the TQMa6x are listed in the following table.
Table 11:
DDR3L SDRAM memory size options
Assembly option
Size
2 × DDR3L 128M16 / ×32
512 Mbyte
2 × DDR3L 256M16 / ×32
1 Gbyte
4 × DDR3L 128M16 / ×64
1 Gbyte
4 × DDR3L 256M16 / ×64
2 Gbyte
The following address range is reserved for the DDR controller in
mode X32 / X64 fixed
:
Table 12:
DDR3L SDRAM address range
Start address
Size
Chip Select
Remark
0x1000_0000
0xFFFF_FFFF
CS0#
3840 Mbyte
