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User's Manual l TQMa6x & TQMa6xP UM 0403 l © 2019, TQ-Systems GmbH
Page 8
3.2.1.5
Boot configuration
Note: Boot configuration
No boot device is preset when the TQMa6x is delivered.
Some general settings are defined by eFuses independent from the boot device.
Table 4:
General boot settings
i.MX6
TQMa6x
eFuse
Option
Setting
Signal
Pin
BOOT_CFG1[7:0]
Boot configuration 1:
Specific to selected boot mode
–
BOOT_CFG1_7:0
–
BOOT_CFG2[7:0]
Boot configuration 2:
Specific to selected boot mode
–
BOOT_CFG2_7:0
–
BOOT_CFG3[7]
L1 I-Cache DISABLE:
0 = Enabled
1 = Disabled
0
BOOT_CFG3_7
X2-97
BOOT_CFG3[6]
BT_MMU_DISABLE:
0 = MMU / L1 D Cache / PL310 enabled
1 = MMU / L1 D Cache / PL310 disabled
0
BOOT_CFG3_6
X2-98
BOOT_CFG3[5]
DDR Memory Map Config:
00 = Single DDR channel
01 = 2 × 32 Map
10 = 4 KB interleaving
11 = Reserved (Solo / DualLite / Dual / Quad)
11 = Extension Mode (DualPlus / QuadPlus)
(see BOOT_CFG3[1:0])
0
BOOT_CFG3_5
X2-99
BOOT_CFG3[4]
0
BOOT_CFG3_4
X2-100
BOOT_CFG3[3]
Reserved
0
BOOT_CFG3_3
X2-101
BOOT_CFG3[2]
Boot Frequencies ARM / DDR / AXI:
Solo / DualLite:
0 = 792 / 396 / 264 MHz
1 = 396 / 352 / 176 MHz
Dual / Quad / DualPlus / QuadPlus:
0 = 792 / 528 / 264 MHz
1 = 396 / 352 / 176 MHz
0
BOOT_CFG3_2
X2-102
BOOT_CFG3[1]
DDR Memory Map Extension Config:
Quad-Plus/Dual-Plus:
00 = Single DDR Channel / NOC disabled / MMDC reorder enabled
01 = Fixed 2x32 mapping / NOC enabled / MMDC reorder disabled
10 = Reserved
11 = Reserved
Quad/Dual:
Reserved
DualLite/Solo:
Disable SDMMC Manufacture mode:
x0 = Enable
x1 = Disable
0
BOOT_CFG3_1
X2-103
BOOT_CFG3[0]
0
BOOT_CFG3_0
X2-104
BOOT_CFG4[7]
Debug loop:
0 = Loop disabled
1 = Loop enabled
0
BOOT_CFG4_7
X2-85
BOOT_CFG4[6:0]
Boot configuration 4:
Specific to selected boot mode
–
BOOT_CFG4_6:0
–
3:
Voltage level or condition of eFuse.
4:
Only valid when BOOT_CFG3[5:4] = 0b11.
5:
BOOT_CFG3[1] = Reserved