Toshiba TXZ Reference Manual Download

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TXZ Family

Flash Memory

2018-06-05

95 / 120

Rev. 2.0

Figure 6.15 Serial operation mode determination flowchart

6.6.6.2. Acknowledgement Response Data

The internal boot program represents processing states in specific codes and sends them to the controller. From

“Table 6.8

ACK response data corresponding to serial operation determination data” to “Table 6.11 ACK

response data corresponding to flash memory erasing operation” response to each receive data.

The upper four bits of ACK response data are equal to the upper four bits of the operation command data. The bit 3

indicates a receive error. The bit 0 indicates an invalid operation command error, a checksum error or a password

error. The bit 1 and bit 2 are always “0”.

Table 6.8 ACK response data corresponding to serial operation determination data

Transmit data

Meaning

0x86

Determined that UART communication is possible.

(Note)

Note: When the serial operation is determined as UART, if the baud rate setting is determined as unacceptable,

the boot program aborts without sending back any response.

Table 6.9 ACK response data corresponding to operation command data

Transmit data

Meaning

0x?8(Note)

A receive error occurs in the operation command

data.

0x?1(Note)

An undefined operation command data is received

normally.

0x10

Determined as a RAM transfer command.

0x40

Determined as a flash memory erasing command.

Note: The upper 4 bits of the ACK response data are the same as those of the previous command data.

Summary of Contents for TXZ

Page 1: ...8 06 05 1 120 Rev 2 0 2018 Toshiba Electronic Devices Storage Corporation 2018 06 32 bit RISC Microcontroller TXZ Family Reference Manual Flash Memory Code Flash 1 5MB 1 0MB 768KB 512KB Data Flash 32KB FLASH15MHD32 A Revision 2 0 ...

Page 2: ...ata Flash 28 2 3 5 Memory Capacity and the Configuration 28 3 Function Description and Functional Explanations 29 Code Flash 30 3 1 1 Command Sequence 30 3 1 1 1 List of Command Sequence 30 3 1 1 2 Address Bit Configuration in the Bus Write Cycle Code Flash 32 3 1 1 3 Area Address AA Block Address BA Code Flash 34 3 1 1 4 Protect Bit Assignment PBA Code flash 34 3 1 1 5 ID Read Code IA ID Code Fla...

Page 3: ... 1 5 Completion Detection of the Automatic Operation 60 4 1 5 1 Procedure 60 4 1 6 Protection Function 61 4 1 6 1 How to Set the Protection Function 61 4 1 6 2 Protection Release 61 4 1 6 3 Protection Temporary Release Function 61 4 1 7 Security Function 62 4 1 7 1 Security Setting 62 4 1 7 2 Security Setting Release 62 4 1 7 3 Operation 62 4 1 8 Memory Swap Function 63 4 1 8 1 Memory Swap Setting...

Page 4: ...STSCLR Flash Status Clear Register 79 5 2 20 FCBNKCR Flash Bank Change Register 80 5 2 21 FCBUFDISCLR Flash Buffer Disable and Clear Register 80 6 The programming method 81 Initialization 81 Mode Description 81 Mode Determination 82 Memory Map in Each Mode 82 How to Reprogramming the Flash 82 6 5 1 1 A Procedure that a Programming Routine Stored in Flash memory 83 6 5 1 1 Step 1 83 6 5 1 2 Step 2 ...

Page 5: ...the Flash Using Reprogramming Algorithm in Boot ROM 105 6 6 11 1 Step 1 105 6 6 11 2 Step 2 105 6 6 11 3 Step 3 106 6 6 11 4 Step 4 106 6 6 11 5 Step 5 107 6 6 11 6 Step 6 107 How to Reprogramming using Dual Mode 108 6 7 1 Example of Flash Memory Reprogramming Procedure 108 6 7 1 1 Step 1 108 6 7 1 2 Step 2 109 6 7 1 3 Step 3 109 6 7 1 4 Step 4 110 6 7 1 5 Step 5 110 How to Reprogramming User Boot...

Page 6: ...rocedure that a Programming Routine is Transferred from External Host 5 88 Figure 6 12 Procedure that a Programming Routine is Transferred from External Host 6 89 Figure 6 13 Serial operation mode determination data 93 Figure 6 14 Reception flowchart in serial operation mode 94 Figure 6 15 Serial operation mode determination flowchart 95 Figure 6 16 Password configuration Example of Transmission 9...

Page 7: ...ble 3 6 Setting values assigned to FCSWPSR using Memory Swap command and example of address 36 Table 3 7 Command sequence Data flash 37 Table 3 8 Address bit configuration in the bus write cycle data flash 38 Table 3 9 Protect bit program address Data flash 40 Table 3 10 ID Read command code assignment and the contents Data flash 40 Table 4 1 Flash memory function 51 Table 4 2 Detection of Complet...

Page 8: ...amily Flash Memory 2018 06 05 8 120 Rev 2 0 Preface Related documents Document name Clock Control and Operation Mode Exception Input Output Ports Product Information Asynchronous Serial Communication Circuit ...

Page 9: ...A T32A1RUNA T32A2RUNA T32AxRUNA The bit range of a register is written like as m n Example Bit 3 0 expresses the range of bit 3 to 0 The configuration value of a register is expressed by either the hexadecimal number or the binary number Example ABCD EFG 0x01 hexadecimal XYZn VW 1 binary Word and Byte represent the following bit length Byte 8 bits Half word 16 bits Word 32 bits Double word 64 bits...

Page 10: ...e Technology Inc Super Flash is registered trademark of Silicon Storage Technology Inc All other company names product names and service names mentioned herein may be trademarks of their respective companies Arm Cortex and Thumb are registered trademarks of Arm Limited or its subsidiaries in the US and or elsewhere All rights reserved ...

Page 11: ...rms and Abbreviation Some of abbreviations used in this document are as follows ACK Acknowledgement Addr Address Adr Address BLK Block KB Kilo Bytes PG Page POR Power On Reset SFR Special Function Register UART Universal Asynchronous Receiver Transmitter ...

Page 12: ...ytes Automatic chip erasing Erasing of all the area of a flash memory is performed automatically Object Code flash Data flash Except User information area in code flash Automatic area erasing Erasing in an area unit is performed automatically Automatic block erasing Erasing in a block unit is performed automatically Automatic page erasing Erasing in a page unit is performed automatically Program e...

Page 13: ...not be performed Table 1 3 Functional description data flash Flash memory Function classification Function Functional Description Comments Data Flash 32KB Programming and Erasing Automatic Programming Data programming is performed at 1 words 4 bytes Automatic area erasing Erasing in an area unit is performed automatically Automatic block erasing Erasing in a block unit is performed automatically A...

Page 14: ... RAM 194KB 0x00180000 0x00001800 0x00000000 Single Boot Mode Single Chip Mode CODE FLASH 1536KB BOOT ROM DATA FLASH 32KB BOOT ROM 6KB code SRAM Peripheral DATA FLASH 32KB CODE FLASH Mirror 1536KB FLASH SFR BOOT ROM Mirror CODE FLASH Mirror 1536KB フラッシュ SFR FLASH SFR Flash domain Mirror Code Flash Programming Erasing Read Flash domain Data Data Flash Programming Erasing Read Flash domain Code Code ...

Page 15: ...L Flash Control Register FCCR Flash Status Clear Register FCSTSCLR Data Flash Data Flash interface FLASH I F2 Code Flash0 Read buffer Flash Bank Change Register FCBNKCR Flash Buffer Disable and Clear Register FCBUFDISCLR Control circuit for Data Flash Include automatic sequence control circuit User Information Area Protect bit Protect bit Security bit Memory SWAP bit KEYCODE Flash Protect Mask Reg...

Page 16: ...00 0x5E004FFF 4 PG5 0x00005000 0x00005FFF 0x5E005000 0x5E005FFF 4 PG6 0x00006000 0x00006FFF 0x5E006000 0x5E006FFF 4 PG7 0x00007000 0x00007FFF 0x5E007000 0x5E007FFF 4 Block1 0x00008000 0x0000FFFF 0x5E008000 0x5E00FFFF 32 Block2 0x00010000 0x00017FFF 0x5E010000 0x5E017FFF 32 Block3 0x00018000 0x0001FFFF 0x5E018000 0x5E01FFFF 32 Block4 0x00020000 0x00027FFF 0x5E020000 0x5E027FFF 32 Block5 0x00028000 ...

Page 17: ...5E102000 0x5E102FFF 4 PG3 0x00103000 0x00103FFF 0x5E103000 0x5E103FFF 4 PG4 0x00104000 0x00104FFF 0x5E104000 0x5E104FFF 4 PG5 0x00105000 0x00105FFF 0x5E105000 0x5E105FFF 4 PG6 0x00106000 0x00106FFF 0x5E106000 0x5E106FFF 4 PG7 0x00107000 0x00107FFF 0x5E107000 0x5E107FFF 4 Block1 0x00108000 0x0010FFFF 0x5E108000 0x5E10FFFF 32 Block2 0x00110000 0x00117FFF 0x5E110000 0x5E117FFF 32 Block3 0x00118000 0x...

Page 18: ...32 Block10 0x00050000 0x00057FFF 0x5E050000 0x5E057FFF 32 Block11 0x00058000 0x0005FFFF 0x5E058000 0x5E05FFFF 32 Block12 0x00060000 0x00067FFF 0x5E060000 0x5E067FFF 32 Block13 0x00068000 0x0006FFFF 0x5E068000 0x5E06FFFF 32 Block14 0x00070000 0x00077FFF 0x5E070000 0x5E077FFF 32 Block15 0x00078000 0x0007FFFF 0x5E078000 0x5E07FFFF 32 1 Block16 0x00080000 0x00087FFF 0x5E080000 0x5E087FFF 32 Block17 0x...

Page 19: ...FF 32 Block6 0x00030000 0x00037FFF 0x5E030000 0x5E037FFF 32 Block7 0x00038000 0x0003FFFF 0x5E038000 0x5E03FFFF 32 Block8 0x00040000 0x00047FFF 0x5E040000 0x5E047FFF 32 Block9 0x00048000 0x0004FFFF 0x5E048000 0x5E04FFFF 32 Block10 0x00050000 0x00057FFF 0x5E050000 0x5E057FFF 32 Block11 0x00058000 0x0005FFFF 0x5E058000 0x5E05FFFF 32 Block12 0x00060000 0x00067FFF 0x5E060000 0x5E067FFF 32 Block13 0x000...

Page 20: ...E00FFFF 32 Block2 0x00010000 0x00017FFF 0x5E010000 0x5E017FFF 32 Block3 0x00018000 0x0001FFFF 0x5E018000 0x5E01FFFF 32 Block4 0x00020000 0x00027FFF 0x5E020000 0x5E027FFF 32 Block5 0x00028000 0x0002FFFF 0x5E028000 0x5E02FFFF 32 Block6 0x00030000 0x00037FFF 0x5E030000 0x5E037FFF 32 Block7 0x00038000 0x0003FFFF 0x5E038000 0x5E03FFFF 32 Block8 0x00040000 0x00047FFF 0x5E040000 0x5E047FFF 32 Block9 0x00...

Page 21: ...FF 0x5E081000 0x5E081FFF 4 Page130 0x00082000 0x00082FFF 0x5E082000 0x5E082FFF 4 Page131 0x00083000 0x00083FFF 0x5E083000 0x5E083FFF 4 Page132 0x00084000 0x00084FFF 0x5E084000 0x5E084FFF 4 Page133 0x00085000 0x00085FFF 0x5E085000 0x5E085FFF 4 Page134 0x00086000 0x00086FFF 0x5E086000 0x5E086FFF 4 Page135 0x00087000 0x00087FFF 0x5E087000 0x5E087FFF 4 Page252 0x000FC000 0x000FCFFF 0x5E0FC000 0x5E0FCF...

Page 22: ...F 0x5E07C000 0x5E07CFFF 4 Page125 0x0007D000 0x0007DFFF 0x5E07D000 0x5E07DFFF 4 Page126 0x0007E000 0x0007EFFF 0x5E07E000 0x5E07EFFF 4 Page127 0x0007F000 0x0007FFFF 0x5E07F000 0x5E07FFFF 4 1 Page128 0x00080000 0x00080FFF 0x5E080000 0x5E080FFF 4 Page129 0x00081000 0x00081FFF 0x5E081000 0x5E081FFF 4 Page130 0x00082000 0x00082FFF 0x5E082000 0x5E082FFF 4 Page131 0x00083000 0x00083FFF 0x5E083000 0x5E083...

Page 23: ...F 0x5E07C000 0x5E07CFFF 4 Page125 0x0007D000 0x0007DFFF 0x5E07D000 0x5E07DFFF 4 Page126 0x0007E000 0x0007EFFF 0x5E07E000 0x5E07EFFF 4 Page127 0x0007F000 0x0007FFFF 0x5E07F000 0x5E07FFFF 4 1 Page128 0x00080000 0x00080FFF 0x5E080000 0x5E080FFF 4 Page129 0x00081000 0x00081FFF 0x5E081000 0x5E081FFF 4 Page130 0x00082000 0x00082FFF 0x5E082000 0x5E082FFF 4 Page131 0x00083000 0x00083FFF 0x5E083000 0x5E083...

Page 24: ...007FFF 0x5E007000 0x5E007FFF 4 Page124 0x0007C000 0x0007CFFF 0x5E07C000 0x5E07CFFF 4 Page125 0x0007D000 0x0007DFFF 0x5E07D000 0x5E07DFFF 4 Page126 0x0007E000 0x0007EFFF 0x5E07E000 0x5E07EFFF 4 Page127 0x0007F000 0x0007FFFF 0x5E07F000 0x5E07FFFF 4 2 2 4 User Information Area Configuration of Code Flash Table 2 10 User Information Area Configuration of Code Flash FLASH I F Area User information area...

Page 25: ...Note4 32 24 4 192 5 80s 512 512 1 32 16 4 128 3 86s Note1 The time above mentioned is for reference only which calculated the Oscillation frequency of IHOSC1 on the standard 10MHz Typ And indicate the case of the initial value of each register after reset A data transfer time is excluded Note2 Since programming is performed per 4 WORD at one time it is required four times above mentioned Note3 It ...

Page 26: ...unction and a protection function One block size is 4 KB Page It is used by the erase function One page size is 256 byte 2 3 2 Block Configuration of Data Flash Table 2 12 Block configuration of 32 KB data flash FLASH I F Area Block name Program erase read address Block size KB 2 4 Block0 0x30000000 0x30000FFF 4 Block1 0x30001000 0x30001FFF 4 Block2 0x30002000 0x30002FFF 4 Block3 0x30003000 0x3000...

Page 27: ...age3 0x30000300 0x300003FF 256 Page4 0x30000400 0x300004FF 256 Page5 0x30000500 0x300005FF 256 Page6 0x30000600 0x300006FF 256 Page7 0x30000700 0x300007FF 256 Page8 0x30000800 0x300008FF 256 Page9 0x30000900 0x300009FF 256 Page10 0x30000A00 0x30000AFF 256 Page11 0x30000B00 0x30000BFF 256 Page12 0x30000C00 0x30000CFF 256 Page13 0x30000D00 0x30000DFF 256 Page14 0x30000E00 0x30000EFF 256 Page15 0x300...

Page 28: ...ion for detail 2 3 5 Memory Capacity and the Configuration Table 2 14 Memory capacity and the configuration Capacity KB Area Block Page Programming time Note Erasing time Note Size KB pcs Size KB pcs Size Bytes pcs Word Area Page Block Area 32 32 1 4 8 256 128 64 7µs 531ms 1 0ms 15 4ms 9 2ms Note The time above mentioned is for reference only which calculated the Oscillation frequency of IHOSC1 on...

Page 29: ... swap erasing Modified Program erase protect only protection of program is supported Deleted Erase resume suspend function Precautions 1 Make sure to oscillate the internal high speed oscillator1 IHOSC1 when data is programmed or erased code flash data flash user information area Also oscillate the IHOSC1 before the operations related to the flash memory including protection and security operation...

Page 30: ...h bus cycle 5th bus cycle 6th bus cycle 7th bus cycle Address Address Address Address Address Address Address Data Data Data Data Data Data Data Read Reset 0xYYYYXXXX 0xF0 ID Read 0xYYYYX55X 0xYYYYXAAX 0xYYYYX55X IA 0xYYYYXXXX 0xAA 0x55 0x90 0x00 ID Automatic programming 0xYYYYX55X 0xYYYYXAAX 0xYYYYX55X PA PA PA PA 0xAA 0x55 0xA0 PD0 PD1 PD2 PD3 Automatic page erasing 0xYYYYX55X 0xYYYYXAAX 0xYYYYX...

Page 31: ...YYX55X 0xYYYYXAAX 0xYYYYX55X 0xYYYYX55X 0xYYYYXAAX MSA Note 0xAA 0x55 0x80 0xAA 0x55 0x60 Automatic security bit programming 0xYYYYX55X 0xYYYYXAAX 0xYYYYX55X SBA 0xAA 0x55 0x9A 0x9A Automatic security bit erasing 0xYYYYX55X 0xYYYYXAAX 0xYYYYX55X 0xYYYYX55X 0xYYYYXAAX SBA Note 0xAA 0x55 0x80 0xAA 0x55 0x60 Note Please refer to Table 3 3 Address bit configuration in the bus write cycle Code flash Su...

Page 32: ...ormal command 0x5E 000 fixed Area 0 00 1 01 2 10 0 Recommended Command 0 Recommended Read reset ID Read Address Adr 31 24 Adr 23 21 Adr 20 16 Adr 15 14 Adr 13 0 Read reset Address setting of 1st bus write cycle of Read reset 0x5E 000 fixed 0 Recommended ID Read IA ID address address setting of the 4th bus write cycle of ID Read 0x5E 000 fixed 00000 fixed ID address 0 Recommended Automatic chip era...

Page 33: ...ddress 0 Recommended Automatic protect bit programming erasing Address Adr 31 24 Adr 23 21 Adr 20 19 Adr 18 12 Adr 11 4 Adr 3 0 Protect bit erasing PBA Protect Bit Address address setting of the 6th bus write cycle of Protect bit erasing 0x5E 000 fixed FLASH I F 0 00 1 10 0000010 fixed 0 Recommended Protect bit programming PBA Protect Bit Address address setting of the 4th bus write cycle of Prote...

Page 34: ...otect Bit Assignment PBA Code flash A protect bit can be controlled in the unit of one bit Table 3 4 Protect bit programming address shows the protect bit selection of the automatic protect bit programming Table 3 4 Protect bit programming address FLASH I F Area Block Page Register Protect bit PBA 11 4 Example of address 31 0 Adr 11 10 Adr 9 Adr 8 Adr 7 Adr 6 Adr 5 Adr 4 0 0 0 Note 0 FCPSR0 PG0 00...

Page 35: ...0 1 0 0 0 0 0 0x5E002200 26 208 to 215 BLK26 00 1 0 0 0 0 1 0x5E002210 27 216 to 223 BLK27 00 1 0 0 0 1 0 0x5E002220 28 224 to 231 BLK28 00 1 0 0 0 1 1 0x5E002230 29 232 to 239 BLK29 00 1 0 0 1 0 0 0x5E002240 30 240 to 247 BLK30 00 1 0 0 1 0 1 0x5E002250 31 248 to 255 BLK31 00 1 0 0 1 1 0 0x5E002260 1 2 0 Note 0 FCPSR3 PG0 00 0 0 0 0 0 0 0x5E102000 1 PG1 00 0 0 0 0 0 1 0x5E102010 2 PG2 00 0 0 0 0 ...

Page 36: ...cture code 0x0098 00 0x5E000000 Device code 0x005A 01 0x5E004000 Reserved 10 N A Macro code 0x022F 11 0x5E00C000 3 1 1 6 Memory Swap Bit Assignment MSA Table 3 6 Setting values assigned to FCSWPSR using Memory Swap command and example of address shows the setting values of FCSWPSR SWP 1 0 SIZE 5 0 assigned in the 4th bus write cycle of the auto memory swap command Table 3 6 Setting values assigned...

Page 37: ...d 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle 7th bus cycle Address Address Address Address Address Address Address Data Data Data Data Data Data Data Read reset 0xYYYYXXXX 0xF0 ID Read 0xYYYYX55X 0xYYYYXAAX 0xYYYYX55X IA 0xYYYYXXXX 0xAA 0x55 0x90 0x00 ID Automatic programming 0xYYYYX55X 0xYYYYXAAX 0xYYYYX55X PA 0xAA 0x55 0xC0 PD0 Automatic page erasing 0xYY...

Page 38: ...he bus write cycle data flash Normal command Address Adr 31 24 Adr 23 16 Adr 15 Adr 14 12 Adr 11 4 Adr 3 0 Normal command Address setting of bus write cycle of normal command 0x30 00000000 fixed Area Note 0 Recommended Command 0 Recommended Note Use Area fixed to 0 Read reset ID Read Address Adr 31 24 Adr 23 16 Adr 15 Adr 14 13 Adr 12 0 Read reset Address setting of 1st bus write cycle of read res...

Page 39: ... of 4th bus write cycle of programming command 0x30 00000000 fixed Area Note Program address 0 Recommended Note Use Area fixed to 0 Automatic protect bit programming erasing Address Adr 31 24 Adr 23 16 Adr 15 Adr 14 8 Adr 7 2 Adr 1 0 Protect bit erasing Address setting of 6th bus write cycle of protect bit erasing command 0x30 00000000 fixed 0 fixed 0000001 fixed 0 Recommended Protect bit programm...

Page 40: ... 0 0x30000100 1 DBLK1 00 0 0 0 1 0x30000104 2 DBLK2 00 0 0 1 0 0x30000108 3 DBLK3 00 0 0 1 1 0x3000010C 4 DBLK4 00 0 1 0 0 0x30000110 5 DBLK5 00 0 1 0 1 0x30000114 6 DBLK6 00 0 1 1 0 0x30000118 7 DBLK7 00 0 1 1 1 0x3000011C 3 2 1 5 ID Read Code IA ID Data Flash Table 3 10 ID Read command code assignment and the contents Data flash shows the code assignment and the contents of ID Read command Table...

Page 41: ...rget area of Flash memory by FCAREASEL AREAn FCAREASEL SSFn 1 Automatic programming command sequence Refer to Figure 3 2 FCSR0 RDYBSY 0 FCSR0 RDYBSY 1 Last address Automatic page program end No Yes No Yes No Yes No Yes FCSR0 RDYBSY 1 No Release the target area of Flash memory by FCAREASEL AREAn FCAREASEL SSFn 0 No Figure 3 1 Flowchart of automatic programming 1 ...

Page 42: ...utomatic programming 2 0x5E000550 0x000000AA 0x5E000AA0 0x00000055 0x5E000550 0x000000A0 Program address Program data 32 bit data Program address Program data 32 bit data Program address Program data 32 bit data Program address Program data 32 bit data Automatic programming command sequence address command ...

Page 43: ...ence Automatic chip erasing automatic block erasing automatic page erasing automatic area erasing or automatic code area erasing Refer to Figure 3 4 FCSR0 RDYBSY 0 FCSR0 RDYBSY 1 Automatic erasing end No Yes No Yes No Yes FCSR0 RDYBSY 1 No Yes Release the target area of Flash memory by FCAREASEL AREAn FCAREASEL SSFn 0 No Yes Figure 3 3 Flowchart of automatic erasing 1 ...

Page 44: ...x00000055 Page Address 0x00000040 0x5E000550 0x000000AA 0x5E000AA0 0x00000055 0x5E000550 0x00000080 0x5E000550 0x000000AA 0x5E000AA0 0x00000055 Area Address 0x00000020 0x5E000550 0x000000AA 0x5E000AA0 0x00000055 0x5E000550 0x00000080 0x5E000550 0x000000AA 0x5E000AA0 0x00000055 0x5E000550 0x00000011 Automatic chip erasing command sequence address command Automatic block erasing command sequence Exa...

Page 45: ...command sequence Refer to Figure 3 6 FCSR0 RDYBSY 0 FCSR0 RDYBSY 1 Protect end No Yes No Yes No Yes FCSR0 RDYBSY 1 No Release the target FLASH I F Note of Flash memory by FCAREASEL AREAn FCAREASEL SSFn 0 No Set protect bit of page block by FCPMRm MSKn Note1 Figure 3 5 Flowchart of protect 1 Note1 MSKn represents PMn MSKn and DMSKn Note2 When FLASH I F is 0 area selects 0 When FLASH I F is 1 area s...

Page 46: ...9A Protect bit Address 0x0000009A 0x5E000550 0x000000AA 0x5E000AA0 0x00000055 0x5E000550 0x00000080 0x5E000550 0x000000AA 0x5E000AA0 0x00000055 Protect bit Address 0x00000060 Automatic protect bit programming command sequence Example of FLASH I F0 address command Automatic protect bit erasing command sequence Example of FLASH I F0 address command ...

Page 47: ...SEL SSFn 1 Automatic security bit programming command sequence Automatic security bit erasing command sequence Refer to figure 3 8 FCSR0 RDYBSY 0 FCSR0 RDYBSY 1 Security end No Yes No Yes No Yes FCSR0 RDYBSY 1 No Release AREA0 by FCAREASEL AREA0 FCAREASEL SSFn 0 No Set FCBMR SMB Figure 3 7 Flowchart of security 1 ...

Page 48: ...0AA0 0x00000055 0x5E000550 0x0000009A 0x5E001000 0x0000009A 0x5E000550 0x000000AA 0x5E000AA0 0x00000055 0x5E000550 0x00000080 0x5E000550 0x000000AA 0x5E000AA0 0x00000055 0x5E001000 0x00000060 Automatic security programming command sequence address command Automatic security erasing command sequence address command ...

Page 49: ...quence Automatic memory swap erasing command sequence Refer to Figure 3 10 FCSR0 RDYBSY 0 FCSR0 RDYBSY 1 Automatic memory swap end No Yes No Yes No Yes FCSR0 RDYBSY 1 No Release the target FLASH I F Note of Flash memory by FCAREASEL AREAn FCAREASEL SSFn 0 No Figure 3 9 Flowchart of memory swap 1 Note When FLASH I F is 0 area selects 0 When FLASH I F is 1 area selects 2 When FLASH I F is 2 area sel...

Page 50: ...0009A Memory Swap Address 0x0000009A 0x5E000550 0x000000AA 0x5E000AA0 0x00000055 0x5E000550 0x00000080 0x5E000550 0x000000AA 0x5E000AA0 0x00000055 Memory Swap Address 0x00000060 Automatic memory swap programming command sequence Example of FLASH I F0 address command Automatic memory swap erasing command sequence Example of FLASH I F0 address command ...

Page 51: ... the command is input program or erase operation is internally automatically performed Table 4 1 Flash memory function Main functions Description Automatic programming Code flash Program data in 4 word unit 16 bytes automatically Data flash Program data in 1 word unit 4 bytes automatically Automatic chip erasing Erases the entire flash memory at one time automatically Note1 Automatic area erasing ...

Page 52: ...e flash memory is called bus write cycle Each command takes some bus write cycle The flash memory executes automatic operation as long as the address and data in the bus write cycle are performed in the proper order Otherwise the flash memory aborts executing the command and returns to read mode When the user attempts to cancel the command sequence in the middle of the process or inputs the undefi...

Page 53: ...consecutive 1 word 32 bit data transfer instruction 6 If an access is performed to the target Flash memory in each command sequence a bus fault occurs 7 When issuing commands if wrong addresses or data are inputted make sure to issue Read Reset command then return to read mode 8 Confirmation procedure after each command completion is as follows 1 Execute the final bus write cycle 2 Poll until FCSR...

Page 54: ...r more If reprogramming to an address that has already been programmed once the automatic program is needed to be set again after the automatic page erasing automatic block erasing or automatic chip erasing command is executed Another command sequence is not accepted during automatic operation After programmed flash memory returns to command sequence input mode Note1 Programming execute to the sam...

Page 55: ... operation is repeated per page inside a flash memory It takes the time for the number of pages until erasing operation is completed Note 2 Automatic chip erasing cannot be performed continuously When re issue the chip erasing command after once performing a blank check 4 1 3 3 Automatic Area Erasing 1 Operation The automatic area erasing command performs on the specified area If protected pages o...

Page 56: ...ce input mode Another command sequence is not accepted during automatic operation After erased flash memory returns to command sequence input mode 2 How to set The 1st to 5th bus write cycles are the automatic page erasing command sequences The page to be erased is specified in the 6th bus write cycle After the command sequences are input the automatic page erasing starts 4 1 3 6 Automatic Protect...

Page 57: ...tarts All protect bits are erased at one time Whether the protect bits are erased normally please check the FCPSRn 4 1 3 8 Automatic Security Bit Programming 1 Operation The automatic security bit programming set 1 to the security bit When clear 0 to the security bit use the automatic security bit erasing command For details of the security function refer to 4 1 7Security Function Another command ...

Page 58: ...system reset Please check the FCSSR SEC In security state if perform the security bit erasing command sequence data of all addresses of code flash data flash and security bit are erased Security is released after system reset Read all addresses to check whether data of flash and the security bit are erased normally And if necessary perform the automatic protect bit erasing command 4 1 3 10 ID Read...

Page 59: ...o command sequence input mode 2 How to set The 1st to 4th bus write cycles are the automatic memory swap command sequences After the command sequences are input 1 is set to the designation bit of the FCSWPSR Whether the memory swap is programmed normally please check each bit of the FCSWPSR SWP 1 0 SIZE 5 0 4 1 3 13 Automatic Memory Swap Erasing 1 Operation content The automatic memory swap erasin...

Page 60: ...lash programming Erasing Item Signal name Interruption name Completion of the programming erasing operation of a code flash INTFLCRDY0 Code FLASH Ready interruption of FLASH I F0 INTFLCRDY1 Code FLASH Ready interruption of FLASH I F1 Completion of the programming erasing operation of a code flash INTFLDRDY Data FLASH Ready interruption When an automatic chip erasing command sequence is performed f...

Page 61: ...6 1 How to Set the Protection Function In order to enable a protection function a protect bit is set to 1 by a protect bit programming command The protection function is enabled under the condition below 1 FCPMRm MSKn 1 Note 2 Protect bit n 1 At this time the block n is being protected from data programming erasing When check the status of protect bit monitor FCPSRm after set FCPMRm MSKn 1 Note No...

Page 62: ...curity Setting Release To release the security function perform the procedure below 1 FCSBMR SMB 0 2 Set 0 to the security bit with the security bit erasing command While FCSBMR SMB 1 and FCSSR SEC 1 if the security bit erasing command is executed the chip erasing function is executed and then code flash data flash and security bits are erased 4 1 7 3 Operation Table 4 3 shows the flash memory ope...

Page 63: ...and refer to 4 1 3 12Automatic Memory Swap 4 1 8 2 Memory Swap Operation This section explains the basic operation flow of the memory swap For the concrete example of the memory swap operation refer to 6 8How to Reprogramming User Boot Program Release the protection function temporarily when the protection function is valid For details of the protection function temporary release refer to 4 1 6 3P...

Page 64: ...ng command 8 Options if required Erase copied data old original data Reprogram the flash memory data except the swap regions Validate the protection function Validate the security function Figure 4 1 Example of Procedure of Memory Swap 4 1 8 3 Erasing the Memory Swap Information After the memory swap state is released if the user attempts to perform memory swap again initialize the all bits of the...

Page 65: ...tching program on the RAM and make Jump 2 Write 111 to FCBUFDISCLR BUFDISCLR 2 0 3 Write 111 to FCBNKCR BANK0 2 0 4 Read FCBNKCR BANK0 2 0 to confirm whether FCBNKCR BANK0 2 0 is 111 5 Perform the following operation in the user information area Data reading data programming data erasing 6 Write 000 to FCBNKCR BANK0 2 0 7 Read FCBNKCR BANK0 2 0 to confirm whether FCBNKCR BANK0 2 0 is 000 8 Write 0...

Page 66: ...s Register 3 FCPSR3 0x003C Flash Protect Status Register 4 FCPSR4 0x0040 Flash Protect Status Register 6 FCPSR6 0x0048 Flash Protect Mask Register 0 FCPMR0 0x0050 Flash Protect Mask Register 1 FCPMR1 0x0054 Flash Protect Mask Register 3 FCPMR3 0x005C Flash Protect Mask Register 4 FCPMR4 0x0060 Flash Protect Mask Register 6 FCPMR6 0x0068 Flash Status Register 1 FCSR1 0x0100 Flash Memory SWAP Status...

Page 67: ...the specific code 0xA74A9D23 to FCKCR 2 Rewrite the data of FCSBMR SMB within 16 clocks after Procedure 1 5 2 2 FCSSR Flash Security Status Register Bit Bit Symbol After reset Type Function 31 1 0 R Read as 0 0 SEC 0 1 R Security status Indicates security status 1 Secured 0 Not secured The state of security is loaded by a system reset 5 2 3 FCKCR Flash Key Code Register Bit Bit Symbol After reset ...

Page 68: ...RDYBSY0 1 R ReadyBusy flag of Area 0 and Area1 0 In automatic operation 1 Completion of automatic operation 7 1 0 R Read as 0 0 RDYBSY 1 R ReadyBusy flag all flash area 0 In automatic operation 1 Completion of automatic operation ReadyBusy flag indicate when automatic programming command or automatic erasing command is executed This bit indicates automatic operation status When this bit is 0 it in...

Page 69: ... code flash Area 0 1 Protected 0 Not protected This register indicates the protected status of each page from Page0 to Page7 Block0 If one of bits is 1 it indicates that the corresponding page is protected Protected page cannot be erased and programmed The state of protection is loaded by system reset 6 PG6 0 1 R 5 PG5 0 1 R 4 PG4 0 1 R 3 PG3 0 1 R 2 PG2 0 1 R 1 PG1 0 1 R 0 PG0 0 1 R ...

Page 70: ...k is protected Protected block cannot be erased and programmed The state of protection is loaded by system reset 30 BLK30 0 1 R 29 BLK29 0 1 R 28 BLK28 0 1 R 27 BLK27 0 1 R 26 BLK26 0 1 R 25 BLK25 0 1 R 24 BLK24 0 1 R 23 BLK23 0 1 R 22 BLK22 0 1 R 21 BLK21 0 1 R 20 BLK20 0 1 R 19 BLK19 0 1 R 18 BLK18 0 1 R 17 BLK17 0 1 R 16 BLK16 0 1 R 15 BLK15 0 1 R 14 BLK14 0 1 R 13 BLK13 0 1 R 12 BLK12 0 1 R 11...

Page 71: ... R 4 PG4 0 1 R 3 PG3 0 1 R 2 PG2 0 1 R 1 PG1 0 1 R 0 PG0 0 1 R 5 2 8 FCPSR4 Flash Protect Status Register 4 Bit Bit Symbol After reset Type Function 31 16 0 R Read as 0 15 BLK15 0 1 R Protect status of code flash Area 2 1 Protected 0 Not protected This register indicates the protected status of each block from Block1 to Block15 If one of bits is 1 it indicates that the corresponding block is prote...

Page 72: ...reset 6 DBLK6 0 1 R 5 DBLK5 0 1 R 4 DBLK4 0 1 R 3 DBLK3 0 1 R 2 DBLK2 0 1 R 1 DBLK1 0 1 R 0 DBLK0 0 1 R 5 2 10 FCPMR0 Flash Protect Mask Register 0 Bit Bit Symbol After reset Type Function 31 8 0 R Read as 0 7 PM7 1 R W Protect mask status of code flash Area 0 1 Not masked Protected 0 Masked Not protected This register masks each protected page from Page0 to Page7 block0 This register is initializ...

Page 73: ... 1 R W 28 MSK28 1 R W 27 MSK27 1 R W 26 MSK26 1 R W 25 MSK25 1 R W 24 MSK24 1 R W 23 MSK23 1 R W 22 MSK22 1 R W 21 MSK21 1 R W 20 MSK20 1 R W 19 MSK19 1 R W 18 MSK18 1 R W 17 MSK17 1 R W 16 MSK16 1 R W 15 MSK15 1 R W 14 MSK14 1 R W 13 MSK13 1 R W 12 MSK12 1 R W 11 MSK11 1 R W 10 MSK10 1 R W 9 MSK9 1 R W 8 MSK8 1 R W 7 MSK7 1 R W 6 MSK6 1 R W 5 MSK5 1 R W 4 MSK4 1 R W 3 MSK3 1 R W 2 MSK2 1 R W 1 MS...

Page 74: ...ot masked Protected 0 Masked Not protected This register masks each protected page from Page0 to Page7 block0 This register is initialized by a system reset 6 PM6 1 R W 5 PM5 1 R W 4 PM4 1 R W 3 PM3 1 R W 2 PM2 1 R W 1 PM1 1 R W 0 PM0 1 R W Note To rewrite this register follow the procedure below 1 Write the specific code 0xA74A9D23 to FCKCR 2 Rewrite the data of FCPMR3 PMn within 16 clocks after ...

Page 75: ...e flash Area 2 1 Not masked Protected 0 Masked Not protected This register masks each protected page from Block 1 to Block 15 in the unit of block This register is initialized by a system reset 14 MSK14 1 R W 13 MSK13 1 R W 12 MSK12 1 R W 11 MSK11 1 R W 10 MSK10 1 R W 9 MSK9 1 R W 8 MSK8 1 R W 7 MSK7 1 R W 6 MSK6 1 R W 5 MSK5 1 R W 4 MSK4 1 R W 3 MSK3 1 R W 2 MSK2 1 R W 1 MSK1 1 R W 0 0 R Read as ...

Page 76: ...lash memory in the unit of block This register is initialized by a system reset 6 DMSK6 1 R W 5 DMSK5 1 R W 4 DMSK4 1 R W 3 DMSK3 1 R W 2 DMSK2 1 R W 1 DMSK1 1 R W 0 DMSK0 1 R W Note To rewrite this register follow the procedure below 1 Write the specific code 0xA74A9D23 to FCKCR 2 Rewrite the data of FCPMR6 DMSKn within 16 clocks after Procedure 1 5 2 15 FCSR1 Flash Status Register 1 Bit Bit Symb...

Page 77: ...0000 Area Area0 Area1 Other settings than the above are prohibited 7 2 0 R Read as 0 1 0 SWP 1 0 00 R Swap setting 00 Release the swap Initial status 01 Swap is ongoing 10 Prohibited 11 Release the swap Note1 Perform memory swap on the program in the RAM Note2 If 11 is set to SWP 1 0 swap is released If 00 is set to SWP 1 0 swap condition is released and initialized with the automatic swap erasing...

Page 78: ...h flash memory operation commands Note1 111 Selects Area 4 Others Not select Area 4 15 0 R Read as 0 14 12 000 R W Write as 000 11 0 R Read as 0 10 8 AREA2 2 0 000 R W Specify Area 2 of data flash as the target to enter to Command sequence input mode for data programming with flash memory operation commands Note1 111 Selects Area 2 Others Not select Area 2 7 0 R Read as 0 6 4 AREA1 2 0 000 R W Spe...

Page 79: ... 2 0 000 R W Stops the automatic chip erasing 111 Stops the automatic erasing operation 000 Inactive Others Prohibited Note1 Rewrite the contents of this register on the program code in the RAM Note2 To rewrite this register follow the procedure below 1 Write the specific code 0xA74A9D23 to FCKCR 2 Rewrite data of FCCR WEABORT within 16 clocks after Procedure 1 5 2 19 FCSTSCLR Flash Status Clear R...

Page 80: ...he RAM Note 4 Do not access to code flash Area0 except 0x5E005000 to 0x5E005FFF while the user information area is being used 5 2 21 FCBUFDISCLR Flash Buffer Disable and Clear Register Bit Bit Symbol After reset Type Function 31 3 0 R Read as 0 2 0 BUFDISCLR 2 0 000 R W Stops the buffer of code flash and clears the buffer 111 Stops the buffer function and clears the buffer 000 Start the buffer fun...

Page 81: ... to on chip RAM via a communication function and the The programming erasing program for a flash memory can be run Please refer to 6 6 How to Reprogram the Flash in Single Boot Mode Single chip Mode Normal Mode A user s application program is run Moreover a on chip flash memory can be program erase a flash memory programming erasing program in RAM Although it can be operated to all the flash memor...

Page 82: ...ode therefore normal mode in which user application is activated in single chip mode needs to switch to user boot mode for programming flash memory For that reason the user is required to add a mode judgment routine to the reset service routine in the user application program This mode switch condition is required to be constructed according to the user system set condition A flash memory programm...

Page 83: ...on a printed circuit board programmed the following three program routines into an arbitrary flash block using programming equipment such as a flash writer a Mode determination routine A program to determine to switch to user boot mode b Copy routine A program to copy the data described in c to the on chip RAM c Flash programming routine A program to download new program from the external device a...

Page 84: ...hat a Programming Routine Stored in Flash memory 2 Note All products do not support the determination of the transition destination by the deassertion of Power On Reset POR For the details refer to Product Information in Reference manual 6 5 1 3 Step 3 After the device enters the user boot mode the device executes the copy routine b to download the flash programming routine c from the host control...

Page 85: ...mory 4 6 5 1 5 Step 5 The device continues to execute the flash programming routine to download new program data from the host controller and program it into the erased flash block When the programming is completed set the program erase protection of that flash area in the user s program to ON Figure 6 5 Procedure that a Programming Routine Stored in Flash memory 5 b Copy routine c Programming rou...

Page 86: ...ines the conditions e g pin status to enter user boot mode and determines I O used in data transfer Then suitable circuit design and program are created Before installing the device on a printed circuit board programmed the following two program routines into an arbitrary flash block using programming equipment such as a flash writer a Mode determination routine A program to determine to switch to...

Page 87: ...n user boot mode Figure 6 8 Procedure that a Programming Routine is Transferred from External Host 2 Note All products do not support the determination of the transition destination by the deassertion of Power On Reset POR For the details refer to Product Information in Reference manual 6 5 2 3 Step 3 After the device enters user boot mode the device executes the transfer routine b to download the...

Page 88: ... 6 10 Procedure that a Programming Routine is Transferred from External Host 4 6 5 2 5 Step 5 The device continues to execute the programming routine c on the RAM to download new program data from the host controller and programs it into the erased flash blocks When the programming is completed set the program erase protection of that flash area in the user s program to ON Figure 6 11 Procedure th...

Page 89: ...art operation along with the new application program Figure 6 12 Procedure that a Programming Routine is Transferred from External Host 6 Note All products do not support the determination of the transition destination by the deassertion of Power On Reset POR For the details refer to Product Information in Reference manual 0 1 RESET_N Note ...

Page 90: ...ine on the RAM is executed to erasing programming the flash memory Password Any data 8 bytes to 255 bytes in the flash memory can be used as a password If did not match password generate error and stop RAM transfer A part of user memory use for password Flash memory erasing command Flash memory erasing Erases on chip flash memory except user information area regardless of a program erase protect c...

Page 91: ...block setting of the internal boot program operates on the initial settings fc 10MHz Clock are supplied to using function blocks A baud rate is determined by the 32 bit timer T32A mentioned in 6 6 6 1 Serial Operation Mode Determination At this time a baud rate needs to be within the measurable range by the timer The pins used in the internal boot program are shown in Table 6 4 Pins used in the in...

Page 92: ... mode 0x10 RAM transfer 0x40 Flash memory erasing 6 6 5 1 RAM transfer The RAM transfer is to store data from the controller to on chip RAM When the transfer is complete normally a user program starts The memory address of 0x20000400 or later can be used for a user program except 0x20000000 to 0x200003FF where the addresses are used for the boot program The execution start address means the start ...

Page 93: ...on flowchart in serial operation mode the CPU monitors the level of the receive pin and obtains a timer value at the moment when the receive pin s level is changed Therefore the timer values of tAB tAC and tAD have a margin of error Note that if a transfer goes at a high baud rate the CPU may not be able to determine the level of receive pin Figure 6 15 Serial operation mode determination flowchar...

Page 94: ... such situation when UART mode is utilized the controller should determine a time out period where the time is expected to receive an echo back 0x86 from the target board If it fails to obtain that echo back before the time out the controller should consider that the communication is disabled Figure 6 14 Reception flowchart in serial operation mode ...

Page 95: ...ation command error a checksum error or a password error The bit 1 and bit 2 are always 0 Table 6 8 ACK response data corresponding to serial operation determination data Transmit data Meaning 0x86 Determined that UART communication is possible Note Note When the serial operation is determined as UART if the baud rate setting is determined as unacceptable the boot program aborts without sending ba...

Page 96: ...of Password Arbitrary data sequential data greater than 8 bytes or more in the flash memory can be set a password Password verification is performed by the comparison between the password sent from the external controller and the memory data in the MCU where the password is specified 2 Password Configuration A password is comprised of four elements PLEN PNSA PCSA and a password string See Figure 6...

Page 97: ...tes are sequentially detected a password error occurs Password error If a password error occurs from then on the external device cannot communicate with the TXZ To communicate with the TXZ perform reset with the reset pin RESET_N or Power On Reset POR to reboot the TXZ in single boot mode Note All products do not support the determination of the transition destination by the deassertion of Power O...

Page 98: ...d error occurs as long as data remains in data flash In this case perform chip erasing 4 Password Setting Values and Setting Ranges A password must be set according to the condition described in Table 6 12 Password setting values and setting ranges Unless the condition is met a password error occurs Table 6 12 Password setting values and setting ranges Password Blank product Note 1 Non blank produ...

Page 99: ...word verification Then received data password data is verified Unless all N byte data match the password in the flash memory a password error occurs If a password error occurs an ACK response is a password error When the security function is enabled password verification is performed Figure 6 17 Password check flowchart 6 6 6 5 CHECKSUM Calculation The CHECKSUM is calculated by 8 bit addition igno...

Page 100: ...s possible or not If not the program stops and communication is shutdown 2 T C ACK response to serial operation mode Receive data from the controller is ACK response data responding to the 1st byte of serial operation mode setting data If the target determines the setting is possible the target sets the UART Data reception should be enabled before data is programmed to the transmit buffer Normal s...

Page 101: ... address PNSA 4 bytes The controller transmits the address data where the password length is stored 5 C T Password store start address PCSA 4 bytes The controller transmits the start address where the password is stored 6 C T Password string 8 bytes to 255 bytes The controller transmits password data of the code flash If it has been erased the controller transmits dummy data 7 C T CHECKSUM value o...

Page 102: ... controller transmits a CHECKSUM value of transmit data No 9 to 14 16 T C ACK response to a CHECKSUM value Normal 0x10 Abnormal 0x11 Communication error 0x18 The target checks receive data and it sends ACK response data If a receive error exists the target sends ACK response data 0x18 indicating communication error and then returns to the initial state waiting for operation command data If a recei...

Page 103: ...K response data 0x40 indicating normal state and waits for next data 3 C T Erase enable command data 0x54 The controller transmits erase enable command data 0x54 4 T C ACK response to erase enable command data Normal 0x54 Abnormal 0x51 Communication error 0x58 The target checks receive data and it sends ACK response data If receive error exists the target sends ACK response data 0x58 indicating ab...

Page 104: ...ash Memory 2018 06 05 104 120 Rev 2 0 6 6 10 Internal Boot Program General Flowchart This section shows an internal boot program general flowchart Figure 6 18 Boot program general flowchart UART Baud rate Detection ...

Page 105: ...on the host Figure 6 19 Procedure of Using Reprogramming Algorithm in Boot ROM 1 6 6 11 2 Step 2 The user releases the reset by the pin condition setting for single boot mode and boots up on the Boot ROM According to the procedure of boot mode the user transfers the programming routine a via the UART from the source host Password verification is performed against the password in the user applicati...

Page 106: ...programming routine must be stored in the range from 0x20000400 to the end address which can be transmitted of the on chip RAM Figure 6 21 Procedure of Using Reprogramming Algorithm in Boot ROM 3 6 6 11 4 Step 4 The boot program jumps to the programming routine a in the on chip RAM to erase the flash block containing old application program codes the units of erase is arbitrary size Figure 6 22 Pr...

Page 107: ...e transfer path and the source of the transfer The user can create a hardware board and programming routine to suit your particular needs Figure 6 23 Procedure of Using Reprogramming Algorithm in Boot ROM 5 6 6 11 6 Step 6 When programming of Flash memory is completed the user shuts the power once and disconnects the cable connected with the host The user then turns on the power again so that the ...

Page 108: ...fferent areas for programming erasing of the flash memory When you use an exception in a dual mode please mind not to perform accidentally the area which performs programming erasing of a flash memory 6 7 1 Example of Flash Memory Reprogramming Procedure 6 7 1 1 Step 1 A user determines the conditions e g pin status to enter the on board programming and the target FLASH I F in Flash memory to be p...

Page 109: ...ions are met the program jumps to the flash reprogramming routine to transfer to dual mode Figure 6 26 Reprogramming using Dual Mode 2 6 7 1 3 Step 3 After the program jumps to the flash reprogramming routine the program releases the program erase protection in the old user program area and erases the areas in unit of the area block or page Figure 6 27 Reprogramming using Dual Mode 3 FLASH I F 0 F...

Page 110: ...ed set the program erase protection of that flash block in the user program area to ON Figure 6 28 Reprogramming using Dual Mode 4 6 7 1 5 Step 5 Upon reset the flash memory is set to normal mode After reset the CPU will start operation along with the new application program Figure 6 29 Reprogramming using Dual Mode 5 Note All products do not support the determination of the transition destination...

Page 111: ... memory swap function when Flash memory is reprogrammed The following is an example of reprogramming procedure of user boot program Assumed conditions Swap size is 4K bytes Page 1 program is copied from Page 0 6 8 1 Example of Flash Memory Reprogramming Procedure 6 8 1 1 Step 1 The user confirms whether 00 is read from FCSWPSR SWP 1 0 Figure 6 30 Reprogram by User Boot Program 1 ...

Page 112: ...ion status enabled then write 0 to FCPMR0 PM1 for temporary release protection Figure 6 31 Reprogram by User Boot Program 2 6 8 1 3 Step 3 The user transfers the reprogramming routine to the on chip RAM and moves the PC Program Counter to the transferred program Figure 6 32 Reprogram by User Boot Program 3 ...

Page 113: ...he user erases Page 1 and then copy a program of Page 0 to program of Page 1 Figure 6 33 Reprogram by User Boot Program 4 6 8 1 5 Step 5 The automatic memory swap command sets 01 to FCSWPSR SWP 1 0 to swap Page 0 with Page 1 Figure 6 34 Reprogram by User Boot Program 5 ...

Page 114: ...conditioning routine where FCSWPSR SWP 1 0 is set to 01 To Step 7 Figure 6 35 Reprogram by User Boot Program 6 6 8 1 7 Step 7 The user checks FCPSR0 PG1 0 If protection status enabled then write 0 to FCPMR0 PM1 for temporary release protection Figure 6 36 Reprogram by User Boot Program 7 Note Protection function performs to address Then when memory swapped between Page0 and Page1 PG0 PM0 is Page1 ...

Page 115: ...r transfers the flash reprogramming routine to the on chip RAM and then sets the on chip RAM address to PC Program Counter Figure 6 37 Reprogram by User Boot Program 8 6 8 1 9 Step 9 The user programs a new boot program to Page 0 Figure 6 38 Reprogram by User Boot Program 9 ...

Page 116: ... Family Flash Memory 2018 06 05 116 120 Rev 2 0 6 8 1 10 Step 10 The automatic memory swap command sets 11 to FCSWPSR SWP 1 0 to swap release Page 0 and Page 1 Figure 6 39 Reprogram by User Boot Program 10 ...

Page 117: ... Memory 2018 06 05 117 120 Rev 2 0 7 General Precautions Do not perform any operation that is not described in this document Do not access the addresses described in this document that is not assigned to the registers ...

Page 118: ...ng Moved Note in flow chart of Figure 3 3 Modified title of Automatic page erasing command sequence Modified Figure 3 3 title Delete Example of Area0 from flowchart of Automatic code area erasing in Figure 3 4 3 3 3 Protect bit Added this section 3 3 4 Security bit Added this section 3 3 5 Memory Swap Added this section 4 Details of Flash Memory 2nd line Modified FLASH I F0 for example to FLASH I ...

Page 119: ...releasing in 3 Password Setting Releasing Verification Modified User Information Memory to User Information Area 6 6 10 Internal Boot Program General Flowchart Modified UART automatic Port Detection to UART Baud rate Detection Detection Result to UART Detection Result and Calculate baud rate to UART Calculate baud rate in Figure 6 18 6 6 11 6 Step 6 Deleted Single chip mode in Figure 6 24 ...

Page 120: ...ical equipment equipment used for automobiles trains ships and other transportation traffic signaling equipment equipment used to control combustions or explosions safety devices elevators and escalators devices related to electric power and equipment used in finance related fields IF YOU USE PRODUCT FOR UNINTENDED USE TOSHIBA ASSUMES NO LIABILITY FOR PRODUCT For details please contact your TOSHIB...

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