TXZ Family
Flash Memory
2018-06-05
34 / 120
Rev. 2.0
[Automatic security bit programming/erasing]
Address
Adr
[31:24]
Adr
[23:19]
Adr
[18:17]
Adr
[16:12]
Adr
[11:0]
Security bit
Erasing
SBA: Address of
the 6
th
bus write cycle of security bit erasing
0x5E
“00000”
fixed
“00”
fixed
“00001”
fixed
"0”
Recommended
Security bit
programming
SBA: Address of
the 4
th
bus write cycle of security bit programming
0x5E
“00000”
fixed
“00”
fixed
“00001”
fixed
"0”
Recommended
3.1.1.3. Area Address (AA), Block Address (BA): Code Flash
Table 2.2 to Table 2.5 show area addresses and block addresses. An address of the area or block to be erased should
be specified in the 6
th
bus write cycle of automatic area erasing command and automatic block erasing command. In
single chip mode, an address of the mirror area should be specified.
3.1.1.4. Protect Bit Assignment (PBA): Code flash
A protect bit can be controlled in the unit of one bit.
“Table 3.4
Protect bit programming address” shows the protect bit selection of the automatic protect bit
programming.
Table 3.4 Protect bit programming address
FLASH
I/F
Area
Block
Page
Register
Protect
bit
PBA[11:4]
Example of
address
[31:0]
Adr
[11:10]
Adr
[9]
Adr
[8]
Adr
[7]
Adr
[6]
Adr
[5]
Adr
[4]
0
0
0
(Note)
0
[FCPSR0]
<PG0>
00
0
0
0
0
0
0
0x5E002000
1
<PG1>
00
0
0
0
0
0
1
0x5E002010
2
<PG2>
00
0
0
0
0
1
0
0x5E002020
3
<PG3>
00
0
0
0
0
1
1
0x5E002030
4
<PG4>
00
0
0
0
1
0
0
0x5E002040
5
<PG5>
00
0
0
0
1
0
1
0x5E002050
6
<PG6>
00
0
0
0
1
1
0
0x5E002060
7
<PG7>
00
0
0
0
1
1
1
0x5E002070
1
8 to 15
[FCPSR1]
<BLK1>
00
0
0
1
0
0
0
0x5E002080
2
16 to 23
<BLK2>
00
0
0
1
0
0
1
0x5E002090
3
24 to 31
<BLK3>
00
0
0
1
0
1
0
0x5E0020A0
4
32 to 39
<BLK4>
00
0
0
1
0
1
1
0x5E0020B0
5
40 to 47
<BLK5>
00
0
0
1
1
0
0
0x5E0020C0
6
48 to 55
<BLK6>
00
0
0
1
1
0
1
0x5E0020D0
7
56 to 63
<BLK7>
00
0
0
1
1
1
0
0x5E0020E0
8
64 to 71
<BLK8>
00
0
0
1
1
1
1
0x5E0020F0
