Toshiba SD-2550A, Service Manual

Page: 82 / 109

3-23
Table 3-5-4 TMP94C251AF(Z) (1/5)
Pin
No.
70
|
77
79
|
86
108
|
115
99
|
106
90
|
97
68
67
66
65
64
63
62
60
Function
Port 0: I/O port
Data 0~7: data bus 0~7
Initialized to this function in the external
ROM type, TMP94C251A.
Becomes high impedance when not
accessing to the external memory.
Port 1: I/O port
Data 8~15: data bus 8~15
Initialized to this function when starting with
data bus width higher than 16 bit in the
external ROM type, TMP94C251A.
Becomes to high impedance when not
accessing to the external memory.
Port 4: I/O port
Address 0~7: address bus 0~7
Initialized to this function in the external
ROM type, TMP94C251A.
The signal does not change when not
accessing to the external memory.
Port 5: I/O port
Address 8~15: address bus 8~15
Initialized to this function in the external
ROM type, TMP94C251A.
The signal does not change when not
accessing to the external memory.
Port 6: I/O port
Address 16~23: address bus 16~23
Initialized to this function in the external
ROM type, TMP94C251A.
The signal does not change when not
accessing to the external memory.
Port 70: Output port (initialized to “1”
output)
Read: Strobe signal, which reads the
external memory.
Develops no strobe signal when not
accessing to the external memory.
Initialized to this function in the external
ROM type, TMP94C251A.
Port 71: Output port (initialized to “1”
output)
Write: Strobe signal, which writes D0 ~ D7
of the external memory.
Develops no strobe signal when not
accessing to the external memory.
Port 72: Output port (initialized to “1”
output)
Write: Strobe signal, which writes D8 ~ D15
of the external memory.
Develops no strobe signal when not
accessing to the external memory.
Port 73: Output port (initialized to “1”
output)
Port 74: Output port (initialized to “1”
output)
Port 75: I/O port
Bus request: Signal, which requests to set
the memory interface terminal to high
impedance.
The following terminals become high
impedance. But the state does not change
while functioning as port.
A0~A23, D0~D15, RD, WRLL, WRLH,
CS0~CS5, OE0~OE1, WE0~WE1, RAS
group, CAS group
Port 76: Output port (initialized to “1”
output)
Bus Acknowledge: Signal, which indicates
that BUSRQ request is received.
Port 80: Output port (initialized to “1”
output)
Chip select 0: Develops “L” level when the
address is within the assigned address
area.
Name
P00~P07
D0~D7
P10~P17
D8~D15
P40~P47
A0~A7
P50~P57
A8~A15
P60~P67
A16~A23
P70
RD
P71
WRL
P72
WRH
P73
P74
P75
BUSRQ
P76
BUSAK
P80
CS0
Table 3-5-4 TMP94C251AF(Z) (2/5)
Pin
No.
59
58
57
56
55
29
49
50
51
52
53
44
45
Function
Port 81: Output (initialized to “1” output)
Chip select 1: Develops “L” level when the
address is within the assigned address
area.
Low address strobe 0: Develops RAS
strobe signal for DRAM when the address
is within the assigned address area.
Port 82: Output port (initialized to “1”
output)
Chip select 2: Develops “L” level when the
address is within the assigned address
area.
Port 83: Output port (initialized to “1”
output)
Chip select 3: Develops “L” level when the
address is within the assigned address
area.
Low address strobe 1: Develops RAS
strobe signal for DRAM when the address
is within the assigned address area.
Port 84: Output port (initialized to “1”
output)
Chip select 4: Develops “L” level when the
address is within the assigned address
area.
Port 85: Output port (initialized to “1”
output)
Chip select 5: Develops “L” level when the
address is within the assigned address
area.
Port 86: I/O port
Wait: Bus wait request signal
Port A0: Output port (initialized to “1”
output)
Column address strobe 0: Develops CAS
strobe signal for DRAM when the address
is within the assigned address area.
Lower column address strobe 0: Develops
lower CAS strobe signal for DRAM when
the address is within the assigned address
area.
Port A1: Output port (initialized to “1”
output)
Upper column address strobe 0: Develops
upper CAS strobe signal for DRAM when
the address is within the assigned address
area.
Port A2: Output port (initialized to “1”
output)
Out enable 0: Develops out enable signal
for DRAM.
Port A3: Output port (initialized to “1”
output)
Out enable 1: Develops out enable signal
for DRAM.
Port A4: Output port (initialized to “1”
output)
Write enable 0: Develops write enable
signal for DRAM.
Port B0: Output port (initialized to “1”
output)
Column address strobe 1: Develops CAS
strobe signal for DRAM when the address
is within the assigned address area.
Lower column address strobe 1: Develops
lower CAS strobe signal for DRAM when
the address is within the assigned address
area.
Port B1: Output port (initialized to “1”
output)
Upper column address strobe 1: Develops
upper CAS strobe signal for DRAM when
the address is within the assigned address
area.
Name
P81
CS1
RAS0
P82
CS2
P83
CS3
RAS1
P84
CS4
P85
CS5
P86
WAIT
PA0
CAS0
LCAS0
PA1
UCAS0
PA2
OE0
PA3
OE1
PA4
WE0
PB0
CAS1
LCAS1
PB1
UCAS1