Toshiba SD-2550A, Service Manual

Page: 84 / 109

3-25
Table 3-5-4 TMP94C251AF(Z) (5/5)
Pin
No.
142
141
144
143
36
34
5,
27,
43,
61,
78,
88,
98,
116
14,
37,
54,
69,
87,
89,
107,
130
Function
10 bit AD converter power supply terminal
10 bit AD converter GND terminal (0V)
8 bit DA converter power supply terminal
8 bit DA converter GND terminal (0V)
Power supply terminal for clock doubler.
GND terminal for clock doubler.
Digital power supply terminal (+5V)
Digital GND terminal (0V)
Name
ADVCC
ADVSS
DAVCC
DAVSS
CLVCC
CLVSS
DVCC
DVSS
Table 3-5-5 ZR36732 (1/5)
Pin
No.
124
122
160
2
1
4
20
|
25,
17,
18
9,
11,
13,
15
8
7
6
5
27
|
30
32
31
34
Function
Reset input (active: low). Initializing
process of the device will start when
deasserting is performed after asserting.
Standby input (active: low). When asserting
in accordance with RESET#, all the output
pins and bidirectional pins enter the float
state, and the device is electrically cut off.
All internal operations stop and the power
consumption can be minimized. At standby,
contents of SDRAM and setup parameters
are not preserved.
Display output of Idle, Init or Reset state
(active high). After reset, the device enters
the active state.
Determines the data bus width of host
interface. Only during reset, modification
will be available. At low level (GNDP), the
host interface of the device is set to 2 or 8
bit width, at high level (VDDP) is set to 16
bit width.
Determines the bite order of host interface
data bus at 16 bit width (HWID is VDDP).
Only during reset, modification will be
available. Sets the device so that m.s. bite
is entered/developed by HD [15:8] at low
level (GNDP), and m.s. bite is done by HD
[7:0] at high level (VDDP).
Connects to GNDP when HWID is at GND
level.
Determines protocol of the host bus. Only
during reset, modification will be available.
Sets the device to type A at low level
(GNDP) and type B at high level (VDDP).
8 l.s of the host data bus. When connecting
HWID input to GNDP, only the 8 l.s. signal
is defined as a host data signal. When
connecting HWID to VDDP, the connection
is used as a 8 l.s. line of 16 bit data bus.
When connecting HWID to VDDP, the
connection is used as 11:8 data line of 16
bit host data bus.
When connecting HWID to VDDP, the
connection is used as 15:12 data line of 16
bit host data bus. When connecting HWID
to GNDP, the connection is used as CD-
DSP serial input port pin as defined below.
CD-DSP bit clock input.
CD-DSP data input.
CD-DSP LR clock (Frame) input.
CD-DSP data error input.
Host address input. Inputs address signal
which specifies the physical address of the
device.
Host chip select input. Active: low.
Host protocol type A (HTYPE=GNDP): HR/
W#. The input to determine the direction of
host access.
Host protocol type B (HTYPE=VDDP):
HWR#. Host write input (Active: low).
Host protocol type A (HTYPE=GNDP):
HDS#. Data strobe input (Active: low).
Host protocol type B (HTYPE=VDDP):
HRD#. Host read in input (Active: low).
Name
RESET#
STDBY#
IDLE
HWID
HORD
HTYPE
HD[7:0]
(HD[7:4])
(HD[3])
(HD[2:1])
(HD[0])
HD[11:8]
(HD[11])
(HD[10:8])
HD[15:12]
CDCLK
(HD[12])
CDDAT
(HD[13])
CDFRM
(HD[14])
CDERR
(HD[15])
HA[3:0]
HCS#
HWR# (HR/
W#)
HRD#
(HDS#)
Host interface, CD-DSP interface, sub code interface (32 pins)