Toshiba SD-2550A, Service Manual

Page: 85 / 109

3-26
Table 3-5-5 ZR36732 (2/5)
Pin
No.
36
37
39
134
145
143
120
117
119
118
115
102
105
106
103
108
Function
Host ready output (active: high). When
transmitting a stream through host bus with
this signal, use the signal. And an external
pull up resistor is required.
Confirm the signal becomes active before
transmitting every packet signal, 1 packet
signal is CodBurstLen byte length
transmission signal. After that, it is
available to write the bit stream signals up
to the CodBurstLen byte to the device
continuously.
Interrupt request (active: low). Deasserted
by host reading the interrupt status resistor
of the device. And also deasserted either
after host masks the interruption with the
interrupt mask resistor of the device or
after reset.
When HIRQ# is not asserted, 3-state
status starts. (External pull up resistor is
required.)
Host aknowledge output (active: Low).
When the type A protocol is used, the
device asserts the output and informs the
completion of read/write cycle.
When the signal is not active, 3-state
status starts. (External pull up resistor is
required.)
When the type B protocol is used, the
signal works as a Wait output signal. When
using a host with high speed
(microprocessor), the signal connection is
not always required.
General bidirectional pin to watch/control
by ADP micro code. After reset, the pin is
defined to use for input. By the ADP
command, setting is available.
General input to be watched by DVP micro
code.
General output to be controlled by DVP
micro code. After reset, the pin develops
Low.
27.000 MHz clock or X’tal input for main
processor.
27.000 MHz master clock input for audio.
In standard use, the pin should be
connected to GCLK.
Output to X’tal connected to GCLK. When
not using X’tal for GCLK, XO is kept
unconnected.
PLL configuration input. During reset,
modification will be available. For general
use, both pins should be connected to
GNDP.
At CVBS, the composite video signal is
developed.
At RGB, G signal is developed.
At YUV, Y signal is developed.
At CVBS, Y signal is developed.
At RGB, R signal is developed.
At YUV, V signal is developed.
At CVBS, C signal is developed.
At RGB, B signal is developed.
At YUV, U signal is developed.
Develops either of CVBS or C signal.
Insert a resistor load for DAC gain
adjustment between GND and DAC.
Name
HRDY
HIRQ#
HACK#
GPIO
GPSI
GPSO
GCLK
GCLK1
XO
PLLCFG
[1:0]
CVBS/G/Y
(DAC A)
Y/R/V
(DAC B)
C/B/U
(DAC C)
CVBS/C
(DAC D)
RSET
GPI/O signal (3 pins)
Analog video port (7 pins)
PLL signal (5 pins)
Table 3-5-5 ZR36732 (3/5)
Pin
No.
111
100
127
92
95
93
96
131
133
136
|
138
113
139
141
151
149
148
152
|
159
150
147
Function
Apply reference voltage for DAC gain
adjustment.
Composite sync output. Only when RGB
analog output is selected, the pin takes
effective. For other case, the pin is fixed to
Low.
Main video clock input or output. 27.000
MHz.
Two-divided VCLKx2 signal. The signal is
used as data and sync signal qualifier.
Horizontal sync bidirectional signal pin. The
polarity and length are programmable.
Vertical sync bidirectional signal pin. The
polarity and length are programmable.
Field identification bidirectional signal pin.
The polarity is programmable.
Audio master clock input/output. The
sampling frequency can be selected
among 384fs, 256fs, 192fs and 128fs.
(programmable)
S/PDIF transmitter output. Available to
connect to DAC as the 4th audio output
(AOUT[3]). After reset, the pin develops
low level signal.
PCM stereo audio serial output for DAC.
After reset, the pin develops low level
signal.
PCM stereo audio serial input for ADC.
AOUT [4:0] and LR clock output of AIN.
The square waveform appears in the
sampling frequency.
The polarity of LR is programmable.
AOUT [4:0] and bit clock output of AIN.
AOUT is developed at the rising and falling
edges of the clock signal and AIN is
latched.
DVD-DSP data request output (polarity
programmable).
DVD-DSP data effective input (polarity
programmable).
DVD-DSP data sector start input (polarity
programmable).
DVD-DSP data input bus.
DVD-DSP data bit strobe (clock) input.
Polarity programmable.
DVD-DSP error input. Polarity
programmable.
Name
VREF
COSYNC
VCLKx2
VCLK
HSYNC
VSYNC
FI
AMCLK
S/PDIF
(AOUT[3])
AOUT[2:0]
AIN
ALRCLK
ABCLK
DVDREQ
DVDVALID
DVDSOS
DVDDAT
[7:0]
DVDSTRB
DVDERR
Digital video port (5 pins)
Digital audio port (8 pins)
DVD-DSP interface (13 pins)