Toshiba D-VR3SU, Service Manual

Page: 145 / 217

Circuit Operating Descriptions
7-45
(3) Tuner Block
A. Low pass filter & high pass filter
This consists of IF trap circuit and UHF & VHF separation circuit. If the input signal is IF(45.75MHz), this filter
prevents interference.
B. Single tune & RF AMP
This consists of a filter circuit, RF AMP, impedance conversion circuit, image trap and a single tuning circuit. It
prevents noise and other interference signals. RF AMP is controlled by AGC come from IF DEMOD block.
C. Double tune
It consists of a double tuning circuit to improve rejection characteristic which results in a better band characteris-
tic.
D. MOP IC (Mixer, OSC, PLL)
It consists a VHS and UHF OSC and mixer circuit. We applied a double balance mixer to have better rejection
characteristic, it shows especially various beat characteristic.
It serects channels and contains charge pump band driver. The minimum step standard frequency 31.25KHZ.
AGC
from IF Section
Prescaler
REF
C.P. LPF
Tu voltage
out
Fsc IN Tu Clock Data +B
IF
to IF Section
VL
VH
U
BAND SW
MOP IC
CXA3250AN (SONY)
SN761672A (TEXAS Instruments)
MOP IC
!
SONY : CSA3250AN
@
T I : SN761672A
FROM
MD SECTION
L.P.F
H.P.F
S.T(VL)
S.T(U)
S.T(VL) D.T(VL)
V.MIX
VHF
OSD
UHF
OSD
OSC
AMP
IF
AMP
U.MIX
IF S.T
D.T(VH)
D.T(U)
V.RF Amp
U.RF Amp
H.P.F
+
IF trap
Fig. 7-30 Tuner Section Block Diagram