168
Boards
© Tibbo Technology Inc.
A/D control lines
Nine lines of the
network board) control the A/D
converter. In the table below, "output" means an output of the EM1000, and "input"
means an input of the EM1000:
Line
Function
Corresponding
EM1000 I/O
IC1000
cable line
DO (output)
Serial data out
GPIO13
27
DI (input)
Serial data in
GPIO12
25
CLOCK (output)
Serial clock
(LOW idle state)
GPIO2
5
C/D (output)
Register selection:
HIGH - data register
LOW - control register
GPIO40
6
RFS (output)
Receive frame sync
(Active LOW)
GPIO32
30
TFS (output)
Transmit frame sync
(active LOW)
GPIO33
28
CHS0 (output)
Channel selection, bit 0
GPIO41
8
CHS1 (output)
Channel selection, bit 1
GPIO42
10
CHS2 (output)
Channel selection, bit 2
GPIO43
12
The A/D converter has a 24-bit configuration register, and a 24-bit data register
that contains the A/D conversion result. These registers are accessed through the
serial interface consisting of 5 I/O lines:
·
Two lines -- RFS and TFS -- are used for selecting the transaction type. Inactive
state for these signals is HIGH. The RFS line must be set LOW prior to the read
transaction and remain LOW for the entire transaction duration. The TFS line must
be set LOW prior to the write transaction and remain LOW for the entire
transaction duration.
·
The CLOCK line is used both for writing to and reading from the converter. The
inactive state for this line is LOW. Each read and write "transaction" consists of
24 clock pulses, after which the clock returns to the LOW state. Alternatively, the
IC can be programmed for 16-bit resolution, in which case each transaction will
consist of 16 pulses.
·
The DO line is for sending the data to the converter (writing to the configuration
register). Each data bit must be placed on the DO line while the CLOCK is LOW.
This means that the first, most significant bit, of data must be placed on the DO
line before the first clock pulse of the transaction. Switching the CLOCK from LOW
to HIGH will latch the bit into the converter.
·
The DI line serves double purpose. Before the RFS line is brought LOW, the DI
input indicates whether new measurement data is ready. The DI line is HIGH while
the converter is not ready, and goes LOW when the new data becomes available.
After the RFS line is brought LOW, the DI is used to receive the data from the
converter (read the data register). The most significant bit of the readout is
present on the DI line right after the RFS becomes LOW. The converter will output
next data bit on every HIGH to LOW transition on the CLOCK line. We recommend
that your application records the data while the CLOCK line is HIGH.
