EUROPA SERIES USER MANUAL
21
7-1-5 LVDS_H
LVDS_H digital video includes one clock signal (LVDS_CLK) and 4 data signals
(LVDS_DATA1, LVDS_DATA2, LVDS_DATA3 and LVDS_DATA4). It is convenient to
be parsed by mainstream encode/decode chip.
LVDS digital video can be turned on/off by control commands. When it is turned
on, the output of raw data (ORG), non-uniformity correction (NUC) data, and
dynamic range compression (DRC) data can be selected.
When choosing to use image processing (DRC) data, the core component does
not support the function of electronic zoom and temperature information display.
LVDS Clock Frequency
Model
Clock Frequency
Europa-C 380/
Europa-SL 380
22.500 MHz
Europa-C 640/
Europa-SL 640
33.750 MHz
Europa 380
11.250 MHz
Europa 640
22.500 MHz
CDS_2 Clock Frequency
Model
Clock Frequency
Europa 380
22.5 MHz
Europa 640
45.0 MHz
Note:
1.
The output image data format is YUV, the high 8-bit is Y component, the low 8-bit is UV
component.
2�
“T” stands for temperature data (effective data bits are 14-bits lower, two bits higher
complement 0), “TH” stands for 8-bits higher, and “TL” stands for 8-bits lower.
3.
External synchronization signal mode is adopted. “Vsync” represents frame synchronization
signal and “Hsync” represents row synchronization signal.
4�
The output data of each row is 2 times of the movement surface array N, such as 640x512
movement, each row contains 640x2=1280 clock cycles (N = 640), and each frame contains
512 rows (M=512).
